Metal and interconnect stress is the damage that current, temperature and stress do to the metal lines and vias of a chip, and the breakdown of the dielectric between those lines. This page covers electromigration, the Blech effect, the statistics and design limits used for lines and vias, stress migration of copper vias, and time-dependent breakdown of the low-k dielectric between lines. Heating by the dissipated power is on the Thermal Stress page, the breakdown of gate oxides and the overstress of transistors are on the Electrical Stress page, the forces on joints and packages are on the Mechanical and Package Stress page, and the general statistics of lifetime are on the Failure Rate and the Bathtub Curve page. Electromigration in solder bumps and wires of the package is not covered.
1. Why It Happens
- Trigger: A direct, or net, current through a narrow metal line or via at a raised temperature (Lienig and Jerke); a temperature that differs from the one at which the metal was stress-free, which leaves residual thermal stress (Shohel et al.; Croes et al.); and a voltage between neighbouring lines (Bashir et al.).
- Mechanism, electromigration: The current pushes metal atoms in the direction of the electron flow. At a place where the flux changes, such as a via, a barrier or the end of a line, atoms accumulate or are removed, and a stress gradient builds up that opposes the flux (Rovitto; Ceric). Voids form where atoms leave and hillocks where they arrive, and both can accelerate themselves (Lienig and Jerke). In copper the main diffusion path is the interface between the copper and the SiN top layer (Choi; Wei).
- Mechanism, nucleation and growth: A void nucleates when the stress at the blocked end reaches a threshold (Rovitto; Shohel et al.). It then grows; in a long line the volume grows linearly in time, and in a short line it saturates at a volume set by the steady-state stress (He and Suo). In short copper lines most of the failure time is spent in growth (Dwyer). Pre-existing voids away from the cathode can also grow and drift toward it (Choi).
- Mechanism, vias: A void directly under a via gives an abrupt jump of resistance, and a void displaced along the line or in the line gives a progressive rise (Lee and Oates). The side of the via that the electrons come from matters; in tests of via-above and via-below lines the two geometries differ in lifetime because of the void size needed for failure (Wei). In copper, adjacent segments change the stress of a segment even when they carry no current (Choi), and segments are not fundamental units of reliability (Wei).
- Mechanism, stress migration: Without any current, the stress in the copper and its gradients move vacancies. Below and in vias, interface diffusion driven by a stress gradient and grain-boundary diffusion driven by a vacancy gradient both cause voids, and which one dominates depends on temperature (Croes et al.).
- Mechanism, dielectric breakdown: The field between two lines, V divided by the space, wears out the dielectric until the leakage exceeds a limit (Bashir et al.).
- What sets the rate: The current density and the temperature, with the current exponent and the activation energy (Lienig and Jerke; Wei); the length of the line against the Blech length (Airani and Guttal); the geometry of the via and the metal overlap, the reservoir effect (Lienig and Jerke; Wei); the diffusion path and the microstructure (Dwyer; Choi); the residual stress (Shohel et al.); and for the dielectric the space, the line-width variation and the voltage (Bashir et al.).
- Failure criterion: An abrupt jump or a progressive rise of resistance (Lee and Oates; Wei), where the percentage of rise is set by the test and is not given by the sources read; a leakage current above 100 for the dielectric (Bashir et al.).
2. Where to Look
- Location: Directly under vias when the electrons flow from the upper to the lower level, and inside vias when they flow the other way (Lee and Oates); the cathode end of a line, where atoms leave and voids grow (Choi; He and Suo); long lines carrying direct current at high density, which also have to be compared with the Blech length (Airani and Guttal); junctions where the current is not uniform, such as vias with crowding (Lienig and Jerke); vias connected to line ends, which are more prone to stress voiding than vias in the middle of a large plate (Croes et al.); and two lines at the minimum space that run side by side for a long distance, for dielectric breakdown (Bashir et al.).
- Signature: A sudden resistance jump that points to a slit void under a via; a resistance that rises steadily, which points to a void in the line or beside the via (Lee and Oates; Wei); an open circuit; a hillock (Lienig and Jerke); and for the dielectric a rise of the leakage current between neighbouring lines (Bashir et al.).
- Confirm with: Resistance monitoring of test structures with a bridge circuit of 1 resolution and many links in series (Lee and Oates); a comparison of via-above and via-below structures to find the interface (Wei); and imaging of the void location, which the sources imply but do not describe (my reading). That the failure moves to the other end when the current is reversed is a check from background knowledge.
- Look-alikes: Stress voiding happens without current and so looks like electromigration in a resistance trace (Croes et al.). Voids inside vias can come from the process and can be suppressed by the via barrier and the cleaning (Lee and Oates). Dishing of the polish and necking of the line shorten the life of a critical region (Airani and Guttal). A dielectric failure between lines is made earlier by narrow spaces from line-width variation (Bashir et al.).
3. Prevention
- Design: Size the width of the wire and the number of vias from the equivalent current, with a derating for temperature (Lienig and Jerke; the wire-width row). Use enough metal overlap at vias to keep the reservoir effect (Lienig and Jerke). Do not rely on the Blech length for copper trees and multi-segment lines, where the simple product can give false answers (Shohel et al.; Wei). Keep the current in a via homogeneous so that the factor for crowding stays near 1 (Lienig and Jerke). Keep a margin of space for the dielectric, because a 10 per cent smaller space costs 17 to 36 per cent of life (computed in the dielectric row).
- Material and process: Copper resists electromigration better than aluminium, and an aluminium alloy with silicon and copper is better than pure aluminium (Lienig and Jerke). Bamboo lines, whose grain diameter exceeds the width, are more resistant (Lienig and Jerke). Control the interface between the copper and the top layer, which is the main diffusion path (Choi; Wei; that this is the lever to pull is my reading). Optimise the via barrier and the cleaning to avoid voids in vias (Lee and Oates). Control polishing and etching, which cause dishing and necking (Airani and Guttal).
- Operation: Lower the temperature, since the Arrhenius factor is the largest term of the acceleration. Use alternating or bidirectional currents where the average model applies, since they allow self-healing (Lienig and Jerke).
- Screening and test: Accelerated tests at high temperature and current density with lognormal analysis and an extrapolation with a failure budget (Rovitto; the extrapolation row), with many links in series to reach the low percentiles (Lee and Oates), and with care at low current density where void growth and not nucleation sets the life (Choi). For the dielectric, constant-voltage tests at several fields at 150 with a leakage limit, scaled by the vulnerable length (Bashir et al.).
Electromigration Kinetics
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Atomic flux and drift velocity under current and stress | |||
| Stress evolution in a blocked line and time to void nucleation (Korhonen) | |||
| Void growth, saturation and critical void volume | |||
| Blech criterion, critical product and Blech length |
Lifetime Statistics and Design Limits
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Black’s equation and acceleration factor | |||
| Lognormal distribution of lifetimes and percentile life | |||
| Competing modes and the number of links in a structure | |||
| Extrapolation from stress test to use with a failure budget | |||
| Equivalent current for alternating and pulsed currents | |||
| Wire width, temperature derating and via count |
Stress Migration
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Thermal stress in a confined copper line | |||
| Stress-migration time to failure and temperature of the peak |
Dielectric Breakdown Between Lines
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Dielectric breakdown between lines: field and temperature | |||
| Weibull length scaling and chip-level combination of line-space groups |
Important Questions
Ques: Which current exponent should Black’s equation use?
The sources disagree. Lienig and Jerke give of about 2. Airani and Guttal quote exponents that change with current density, 1 up to 0.1 , 1.5 up to 1 and 2 above, and from a second reference 1.1 plus or minus 0.2 up to 2.5 and 1.8 above. Choi finds that the life follows when pre-existing voids limit it and when nucleation does. Ceric’s page lists = 1 for nucleation and 2 for growth, but its own nucleation time varies as , so I read the list as swapped (my reading). A current ratio of 2.5 gives an acceleration of 2.7 for 1.1, 5.2 for 1.8 and 6.25 for 2 (computed). Near the use current the lower exponents are more likely, because growth then limits the life, so projecting with = 2 overstates the life in use. Reference: Lienig and Jerke, ‘Electromigration-Aware Physical Design of Integrated Circuits’, embedded tutorial, 18th International Conference on VLSI Design (VLSID’05), 2005 (fetch-tool summary; the equations are partly garbled there and are reconstructed); Airani and Guttal, ‘Chip-Level Electromigration Reliability Evaluation with Multiple On-Die Variation Effects’, Micron Technology, arXiv:1712.05562 (year not stated, probably 2015 or later) (fetch-tool summary; the equations are images and were reconstructed there); Z.-S. Choi, ‘Reliability of copper interconnects in integrated circuits’, PhD thesis, Massachusetts Institute of Technology, 2007 (abstract only); H. Ceric, ‘Numerical Techniques in Modern TCAD’, section 4.4 ‘Prediction of the Voids Nucleation Sites’, TU Wien (year not stated) (fetch-tool summary).
Ques: Which activation energy should be used for electromigration?
Wei measured 0.80 plus or minus 0.06 for the drift velocity in dual-damascene copper, He and Suo fitted 0.90 , and Shohel et al. use 0.8 . For stress migration Croes et al. find 0.9 and 1.2 for two different mechanisms. The sizes of the differences matter: between 105 and 300 the Arrhenius factor is 1493 for 0.7 , 12048 for 0.9 and 97223 for 1.1, so the extremes differ by 65 times (computed). Higher values belong to other paths, since copper bulk diffusion is near 2.1 , grain boundaries near 1.2 and the top interface between 0.8 and 1.2 (background knowledge). Lines that fail at the top interface are more likely to show 0.8 to 0.9 , as Wei and He and Suo agree, so 0.9 is the safer middle choice. Reference: F. L. Wei, ‘The electromigration drift velocity and the reliability of dual-damascene copper interconnect trees’, SM thesis, Massachusetts Institute of Technology, 2004 (abstract only); He and Suo, ‘Statistics of Electromigration Lifetime Analyzed Using a Deterministic Transient Model’ (Intel and Harvard; journal and year not stated) (fetch-tool summary; several equations garbled); Al Shohel, Chhabria and Sapatnekar, ‘A New, Computationally Efficient Blech Criterion for Immortality in General Interconnects’, University of Minnesota, arXiv:2105.08784, 2021 (fetch-tool summary); Croes, Wilson, Lofrano, Travaly, De Roest, Tokei and Beyer, ‘Time and temperature dependence of early stage stress-induced-voiding in Cu/low-k interconnects’, IEEE International Reliability Physics Symposium 2009, pp. 457-463 (abstract only).
Ques: Is the Blech product of copper one number?
No. Airani and Guttal give a critical product of 2000 to 10000 and a Blech length of about 10 to 100 , and Shohel et al. use 0.27 , which is 2700 . With their data I get = 2680 (computed). At 1 the first range gives 20 to 100 and the second 27 ; at 3 they give 6.7 to 33 and 9 (computed). Wei finds that true immortality occurs only for very short copper lines at best because voids nucleate easily, and Shohel et al. show that the criterion gives false answers for lines with several segments. The lower end, near 2700 , is the more likely one for a design rule, and it applies only to a single blocked segment (my reading). Reference: Airani and Guttal, ‘Chip-Level Electromigration Reliability Evaluation with Multiple On-Die Variation Effects’, Micron Technology, arXiv:1712.05562 (year not stated, probably 2015 or later) (fetch-tool summary; the equations are images and were reconstructed there); Al Shohel, Chhabria and Sapatnekar, ‘A New, Computationally Efficient Blech Criterion for Immortality in General Interconnects’, University of Minnesota, arXiv:2105.08784, 2021 (fetch-tool summary); F. L. Wei, ‘The electromigration drift velocity and the reliability of dual-damascene copper interconnect trees’, SM thesis, Massachusetts Institute of Technology, 2004 (abstract only).
Ques: Does the effective charge number change the Blech length much?
Yes, and the two sources do not agree. He and Suo use = 0.1 with a resistivity of , and Shohel et al. use 1 with . The stress gradient per unit current density, , is then 54 against 305 , a ratio of 5.6 (computed). At 2.5 the gradient is 1.4 against 7.6 (computed). For the same critical stress the Blech product scales as , so the first set gives a 5.6 times longer immune line. Neither source measures directly; both use model inputs. The set with = 1 is the more conservative, so it is the more likely choice for a design check (my reading). Reference: He and Suo, ‘Statistics of Electromigration Lifetime Analyzed Using a Deterministic Transient Model’ (Intel and Harvard; journal and year not stated) (fetch-tool summary; several equations garbled); Al Shohel, Chhabria and Sapatnekar, ‘A New, Computationally Efficient Blech Criterion for Immortality in General Interconnects’, University of Minnesota, arXiv:2105.08784, 2021 (fetch-tool summary).
Ques: Can a copper line be immortal because the void growth saturates?
In the model of He and Suo the void volume saturates at , so a short line survives if this is below the critical volume. With their numbers, 98 for , the saturated volume is 15, 61 and 333 at lengths of 15, 30 and 70 at 2.5 , and the limit is 38 , or of 36 (computed). Wei writes that immortality from saturation is limited in copper, since without the refractory-metal overlayers of aluminium very small voids at vias can cause failure. If the critical volume were 10 times smaller, the limit would fall to 12 (computed). Wei’s statement makes the small volume more likely, so saturation should not be counted on. Reference: He and Suo, ‘Statistics of Electromigration Lifetime Analyzed Using a Deterministic Transient Model’ (Intel and Harvard; journal and year not stated) (fetch-tool summary; several equations garbled); F. L. Wei, ‘The electromigration drift velocity and the reliability of dual-damascene copper interconnect trees’, SM thesis, Massachusetts Institute of Technology, 2004 (abstract only).
Ques: Which lognormal sigma should be used for projecting the tail?
Lee and Oates report about 0.8 for the abrupt slit-void mode and about 0.4 for the progressive mode, and an effective value of about 0.9 above 0.1 per cent failed that falls to about 0.6 below it. The choice matters at the usual requirement of 0.1 to 0.01 per cent: the life at 0.1 per cent is 0.29 of the median for 0.4, 0.16 for 0.6 and 0.084 for 0.8, and at 0.01 per cent it is 0.23, 0.11 and 0.051 (computed). A projection with 0.4 is thus 4.4 times longer than one with 0.8. Because the abrupt mode dominates the tail, the measured effective values of 0.9 and then 0.6 are more likely than 0.4, and 0.4 describes only the progressive mode. Reference: Lee and Oates, ‘Dominant electromigration failures in copper low-k interconnects’, Silicon Semiconductor, 1 August 2006 (fetch-tool summary; some units are missing there); M. Rovitto, ‘Electromigration Reliability Issue in Interconnects for Three-Dimensional Integration Technologies’, thesis, TU Wien, sections 1.4.4, 2 and 5.2.3 (year not stated) (fetch-tool summaries).
Ques: How do the links of a test structure reach the low percentiles?
Lee and Oates build structures with 10 to 2400 links and report percentiles below per cent. For links in series the failed fraction of the structure is . For 2400 links, a structure fraction of 2.4 per cent corresponds to a single-link fraction of , which is per cent (computed). The median of the structure is the 0.029 per cent point of one link, and a structure fraction of 0.1 per cent needs (computed). This holds only if the links are independent and share one distribution. The source finds that the effective sigma falls below 0.1 per cent, so a straight lognormal line from the median would be wrong in the tail. That effect is more likely than a single sigma, and it favours measuring the tail directly (my reading). Reference: Lee and Oates, ‘Dominant electromigration failures in copper low-k interconnects’, Silicon Semiconductor, 1 August 2006 (fetch-tool summary; some units are missing there).
Ques: Which activation energy and peak temperature apply to stress migration?
Croes et al. find two mechanisms in 80 vias: 0.9 for interface diffusion under a stress gradient, and 1.2 for grain-boundary diffusion under a vacancy gradient. They state that which one dominates depends on temperature, but the abstract does not give the crossover. In the stress-creep form (background knowledge) with an assumed exponent of 2.5, the fastest voiding is at 197 for 0.9 and 208 for 1.2 when the stress-free temperature is 250 , and at 277 for 0.9 when it is 350 (computed). At 100 and 150 the rate is only 0.04 and 0.41 of the peak. The interface is the main diffusion path of copper according to Choi and Wei, so 0.9 is more likely to govern near the peak (my reading). Reference: Croes, Wilson, Lofrano, Travaly, De Roest, Tokei and Beyer, ‘Time and temperature dependence of early stage stress-induced-voiding in Cu/low-k interconnects’, IEEE International Reliability Physics Symposium 2009, pp. 457-463 (abstract only); Z.-S. Choi, ‘Reliability of copper interconnects in integrated circuits’, PhD thesis, Massachusetts Institute of Technology, 2007 (abstract only); F. L. Wei, ‘The electromigration drift velocity and the reliability of dual-damascene copper interconnect trees’, SM thesis, Massachusetts Institute of Technology, 2004 (abstract only).
Ques: Does the E model or the square-root-E model fit the dielectric between lines?
The sources do not decide. Bashir et al. (2011) give both forms, with = 1 and 1/2, and find consistent trends without naming a better fit. Bashir et al. (2010) name an E model and a pE model and fit the life to , but the summary does not define pE, so I do not equate it with either form (my reading). With an assumed 1000 times drop of life between 0.75 and 1.5 and a use field of 0.178 , which is 0.8 over an assumed 45 space, the square-root form projects a life 26.8 times longer than the E form (computed). A 10 per cent narrower space then costs 17 per cent of life in the E form and 36 per cent in the other (computed). The E form is the conservative bound and the safer choice for design (my reading). Reference: Bashir, Milor, Kim and Lim, ‘Methodology to determine the impact of linewidth variation on chip scale copper/low-k backend dielectric breakdown’, Microelectronics Reliability 50 (2010) 1341-1346 (fetch-tool summary; several equations garbled and reconstructed there); Bashir, Kim, Athikulwongse, Lim and Milor, ‘Backend Low-k TDDB Chip Reliability Simulator’, IEEE International Reliability Physics Symposium 2011 (fetch-tool summary; one sign garbled).
Ques: How strongly does the Weibull shape parameter change the dielectric life of a long line?
Bashir et al. (2011) say the shape parameter is typically close to one, and Bashir et al. (2010) estimate 0.81 for a 1X/5X structure against 0.83 from its own curve. The shape sets how the life falls with the vulnerable length, through . A 1000 times longer length shortens the characteristic life by 1000 times for = 1 and by 5055 times for 0.81 (computed). A value of 3 would give only 10 times, which is far from what was measured. The source also finds that decreases for wider lines and depends on the line height, so no single value holds for all spaces. The measured 0.8 is more likely for scaling that structure, and a lower value is the cautious choice for a long line. Reference: Bashir, Kim, Athikulwongse, Lim and Milor, ‘Backend Low-k TDDB Chip Reliability Simulator’, IEEE International Reliability Physics Symposium 2011 (fetch-tool summary; one sign garbled); Bashir, Milor, Kim and Lim, ‘Methodology to determine the impact of linewidth variation on chip scale copper/low-k backend dielectric breakdown’, Microelectronics Reliability 50 (2010) 1341-1346 (fetch-tool summary; several equations garbled and reconstructed there).
Related pages in this vault: Mechanical and Package Stress, Electrical Stress, Thermal Stress, Failure Rate and the Bathtub Curve, Environmental and Chemical, Lognormal Distribution, Interconnect Joule Heating, Electrical Fuses and Antifuses, Wire Resistance and Size Effects, Wafer Curvature Stress Gauge, Electroplating (ECD) Cell.