Thermal stress is the damage and drift caused by the junction temperature of a device, by a temperature that rises on its own because the dissipated power grows with temperature, and by repeated temperature swings. This page covers the heat path, thermal runaway and thermal cycling. The statistics of lifetime are on the Failure Rate and the Bathtub Curve page, and the individual wear-out models (electromigration, oxide breakdown, solder fatigue) belong to the other pages of this folder.
1. Why It Happens
- Trigger: Heat produced in the device that the thermal path to ambient cannot remove, so that the junction runs hotter than the surroundings by ; a high ambient or a poor board adds to it; and repeated heating and cooling of the structure (TI; power-electronics paper).
- Mechanism, steady temperature: The heat flows through a chain of thermal resistances, junction to case, case to sink and sink to ambient, and for a package on a given board (TI). A higher speeds up every thermally activated degradation mechanism; with 0.7 the rate rises by 2.08 for each 10 above 55 and by 1.65 above 125 (computed, from the Arrhenius form on the Failure Rate and the Bathtub Curve page).
- Mechanism, runaway: If the dissipated power rises with temperature, as with the leakage of a reverse-biased diode or the resistance of a conductor, the heat balance has a stable solution only while stays below 1 (Stout; Infineon; the inequality is my derivation). Beyond that the current and the temperature rise together, and only the voltage can stop it (Infineon).
- Mechanism, cycling: Bonded materials expand by different amounts, silicon 4.1, copper 17 and aluminium 24 , so every swing strains the joints (power-electronics paper). The solder under a base plate and the aluminium bond wires on a chip age by fatigue, and the damage raises the thermal resistance or , which raises the heating and hastens the next failure (power-electronics paper).
- What sets the rate: The power and the resistance chain set ; the activation energy sets how fast a mechanism responds; for runaway the product decides; for cycling the swing dominates, a swing of 14 giving an expected life of about cycles and 56 about in one power module (power-electronics paper; the exponent of 4.5 is computed from those two points and also reflects different mean temperatures and cycle times).
- Failure criterion: The junction reaching its rated maximum, 150 with a recommended margin of at least 25 in the example of the power-electronics paper; the loss of a stable operating point in runaway (Stout); or, in cycling, a crack or wire break, or a rise in thermal resistance or (EE Semi; power-electronics paper). The limit for a rise is set by the application and is not given in the sources.
2. Where to Look
- Location: In a gallium-nitride transistor the hot spot lies between the gate and the drain, near the gate, and the hottest point along the gate is at its centre (EDFA article). In a power module look at the solder under the base plate and at the bond wires (power-electronics paper). In a rectifier or Schottky diode under reverse bias look at the junction itself, at high voltage with a poor thermal path (Infineon; Nexperia). The board and the package pad are part of the path, since depends on the board (TI). Wiring leakage, short circuits and insulation defects of oxides show as heat spots (MST).
- Signature: A junction temperature above the prediction for the same power means a degraded heat path, because ageing of the heat-transfer paths raises the thermal resistance (power-electronics paper). A rising points to lifted bond wires (power-electronics paper). In a transistor the drain current and temperature can fall together after electrical stress (EDFA article). Runaway shows as leakage that grows faster than exponentially with ambient and then without bound (Infineon). A failure that appears only at high ambient, low airflow or altitude suggests a thermal-path cause (my reading; TI gives altitude factors of 1.1 to 1.2).
- Confirm with: Micro-Raman gives temperature to plus or minus 5 with a resolution of 0.5 to 0.7 , needs a calibration for each epitaxial structure and was applied to GaN transistors (EDFA article). Thermoreflectance and infrared microscopy are compared for the channel of AlGaN/GaN transistors, where the channel cannot be measured directly and the authors report advantages of thermoreflectance (THERMINIC paper). Lock-in thermal analysis with an infrared detector finds heat-generating areas without opening the package, and a laser method then narrows the fault (MST). The transient thermal impedance gives as the sum of its stages and can be compared with a new device (power-electronics paper; Nexperia). Interim readings at 200 and 500 cycles of a temperature-cycling test show the drift (EE Semi).
- Look-alikes: Other mechanisms also speed up with temperature, so a failure at a high is not proof of a thermal cause; repeat at a lower temperature and the same bias to see whether the rate follows the Arrhenius factor (background knowledge). A rising can also come from the chip metallisation, and a rising thermal resistance can come from the die attach or from the board; the place in the curve where the shift appears points to the layer (background knowledge).
3. Prevention
- Design: Keep a margin below the rated junction temperature, at least 25 in the power-electronics paper, and size the margin for ageing of the heat path (the Infineon example takes from 10 to 15 at end of life). Choose the package and board for low resistance: Nexperia lists 18 on an optimal board and 220 on a standard footprint, and TI shows that a 2s2p test board changes by up to 50 per cent. For a reverse-biased junction check that is below 1 at the worst ambient and voltage (Stout; Infineon; my derivation).
- Material and process: Reduce the mismatch of expansion coefficients where the joint matters, since copper and ceramic differ by a factor of 2 or more and aluminium and silicon by a factor of 6 (power-electronics paper). A higher Schottky barrier of 805 against 665 lowers leakage by about two orders of magnitude (Nexperia), and a device with a lower reference power, typically a larger die, lowers the runaway risk (Stout).
- Operation: Limit the ambient temperature and the reverse voltage, which is the only external variable that interrupts leakage runaway (Infineon), and limit the temperature swing, since the life falls steeply with it (power-electronics paper).
- Screening and test: Temperature cycling with 10 cycles for lot screening and 1000 for qualification, high-temperature storage at 150 for 1000 , operating life at = 125 for 500 to 1000 and burn-in for 48 to 168 (EE Semi). Measure the thermal metrics with the JESD51 methods (TI) and convert the test hours to field hours with the acceleration factor and a mission profile (Failure Rate and the Bathtub Curve page).
Junction Temperature and Thermal Resistance
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Junction temperature from the thermal metrics | |||
| Series thermal chain and the temperature margin | |||
| Transient thermal impedance and pulsed heating | |||
| Temperature-dependent loss and its feedback |
Thermal Runaway
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Temperature dependence of leakage | |||
| Stability criterion for a self-heating device | |||
| Leakage-driven runaway of a reverse-biased diode |
Thermal Cycling and Temperature Tests
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Cycle severity and mismatch strain | |||
| Thermal acceleration of storage and operating-life tests |
Important Questions
Ques: Which metric gives the junction temperature: the junction-to-ambient resistance, the junction-to-case resistance or the junction-to-top parameter?
TI gives for a package on a stated test board, and flags as invalid for system use, since assumes a case that is properly heat sunk. The junction-to-top parameter is not a true resistance, and for plastic packages it is 0.5 to 2 against 4 to 15 for . If the top is measured at 80 with 1 , = 1 gives 81 and = 10 gives 90 (computed, assumed numbers). The reason is that most of the heat leaves through the board and not the top. I regard only for comparison on the standard board, with a measured top temperature, and a board model for the system. Reference: Texas Instruments application report SPRA953, Semiconductor and IC package thermal metrics (year not read) (fetch-tool summary; its equations were garbled and reconstructed there, and it labels the case temperature T_C).
Ques: Is the junction-to-ambient resistance a property of the package, and does 70 or 75 per cent of the heat leave through the board?
TI says that is a function of the package and of many system characteristics, since the test board acts as a heat sink soldered to the leads. It gives two ranges for the share of heat through the board: 70 to 95 per cent for the still-air tests, and 75 to 95 per cent in the discussion. Going from a 1s to a 2s2p board changes by up to 50 per cent, power changes it by a factor of 2 to 3 at very low power, and ambient by about 20 per cent between 0 and 100 . I regard 70 to 95 per cent as the safer range, since it contains the other and the two statements concern different test conditions (my reading). A data-sheet value is therefore a comparison number. Reference: Texas Instruments application report SPRA953, Semiconductor and IC package thermal metrics (year not read) (fetch-tool summary; its equations were garbled and reconstructed there, and it labels the case temperature T_C).
Ques: Does the leakage of a diode double every 10 degrees Celsius?
Stout gives this as a rule of thumb for diodes. The Infineon data for a SiC Schottky diode at 500 , 3 at 25 and 200 at 150 , give = 0.0336 , a doubling every 20.6 (computed). From 25 to 100 the rule gives a factor of 181 and the measured coefficient 12.4 (computed). As an apparent activation energy at 400 the rule means 0.96 and the Infineon data 0.46 (computed). I regard the Infineon figure as more likely for a Schottky diode of that type, because it is a measured pair of points, and the rule as a generic rough value for silicon junctions (my reading, background knowledge). A device with a higher barrier, 805 against 665 , leaks about two orders of magnitude less (Nexperia). Reference: Stout (ON Semiconductor), ‘Predicting thermal runaway - Part 2’, eeNews Europe, 11 September 2011 (fetch-tool summary; the equations were images); Infineon CoolSiC application note on designing with low-barrier Schottky diodes (document number and date not read) (fetch-tool summary); Nexperia application note AN90015 Rev. 1.0 (20 May 2020), reverse-bias safe operating area of rectifiers (fetch-tool summary; equations missing).
Ques: At what ambient does the Infineon diode run away, and what is its junction temperature then?
Infineon reports for 500 , 35 and no conduction loss that runaway starts from an ambient somewhat above 180 , and consistently for junction temperatures above 250 . Writing the fixed-point equation with = 588 per , a solution exists only for not above (computed from the domain of the Lambert function). That gives an ambient of 183.9 , which agrees with the first statement. At that point the leakage is 1.70 , the power 0.85 and the junction 213.7 (computed), not 250 . I regard 214 as the junction temperature at the onset in this model, and the 250 statement as probably describing the unstable branch or a plotted range, which I cannot check from the summary (my reading). Reference: Infineon CoolSiC application note on designing with low-barrier Schottky diodes (document number and date not read) (fetch-tool summary).
Ques: How much margin should be kept below the maximum junction temperature, and does a worse thermal path cost a third or a half of the power?
The power-electronics paper recommends a margin of at least 25 below the 150 limit, and its module example has 31 , with a junction at 119.0 (computed, matching the paper). It also says that ageing of the heat path and parameter drift must be included. For a fixed temperature rise the allowed power scales as , so Infineon’s end-of-life rise from 10 to 15 should cost a third, to 67 per cent (computed). Infineon states almost half. The difference is the leakage: losses that grow with temperature take a share of the allowed power (my reading), so the margin has to cover the feedback as well as the thermal path. I regard the near-half as correct for that circuit and the third as the lower bound for a device without temperature-dependent loss. Reference: ‘Thermal Design of Power Electronic Circuits’, arXiv:1607.01578 (authors and year not read) (fetch-tool summary); Infineon CoolSiC application note on designing with low-barrier Schottky diodes (document number and date not read) (fetch-tool summary).
Ques: How strongly does the temperature swing shorten the life in thermal cycling?
The power-electronics paper gives two module cases: 320 cycles with a 14 swing and an expected life of about cycles, and 100 cycles with a 56 swing and about cycles. A swing four times larger gives a life 500 times shorter, which is an exponent of 4.48 on (computed). The two cases also differ in mean temperature, 75 and 58 , and in cycle duration, so the exponent is only a rough value from two points (my reading). EE Semi says that cycling accelerates fatigue through the swing, the transfer time and the dwell, and gives no exponent. I regard 4.5 only as an indication that the dependence is steep, to be replaced by the exponent of a cycling model when that page is written. Reference: ‘Thermal Design of Power Electronic Circuits’, arXiv:1607.01578 (authors and year not read) (fetch-tool summary); EE Semi, ‘Temperature Cycle Test (TCT)’ and ‘Industry-Standard Reliability Tests’ (fetch-tool summaries; the JEDEC documents were not read).
Ques: Does the activation energy of 0.7 electron-volt apply to every thermal mechanism?
No. The value of 0.7 is the convention of the FIT calculations quoted on the Failure Rate and the Bathtub Curve page, and EE Semi gives no mechanism or activation energy for the storage and operating-life tests. Taking 1000 at 150 and use at 55 , the acceleration factor is 24 for 0.4 , 259 for 0.7 and 2805 for 1.0 , which are 2.7, 29.6 and 320 years (computed). A test that is long enough for one mechanism can therefore be a few years for another. I regard the 0.7 figure as a convention for a typical mixture of defects and the factor as valid only for a mechanism of that energy, and the mechanism pages will give their own values where sources exist (my reading). Reference: EE Semi, ‘Temperature Cycle Test (TCT)’ and ‘Industry-Standard Reliability Tests’ (fetch-tool summaries; the JEDEC documents were not read); Texas Instruments application report SPRA953, Semiconductor and IC package thermal metrics (year not read) (fetch-tool summary; its equations were garbled and reconstructed there, and it labels the case temperature T_C).
Ques: Which method should be used to map the temperature and locate the hot spot?
The sources compare methods by their use. Micro-Raman gives plus or minus 5 with 0.5 to 0.7 resolution, needs a calibration for each epitaxial structure and was used on the GaN transistor to find the hot spot between gate and drain. The THERMINIC abstract says the channel cannot be measured directly, so the surface is measured and simulated, and that thermoreflectance gives temperatures close to the hot spot with advantages over infrared microscopy, without numbers. Lock-in thermal analysis finds heat sources in wiring and oxides without opening the package. I regard Raman or thermoreflectance as the choice for a transistor channel, lock-in analysis as the first step for an unknown fault, and the choice as a trade of resolution, calibration and access (my reading). Reference: Micro-Raman thermography of GaN HEMTs, EDFA Technical Articles 21(2), May 2019 (author not read) (fetch-tool summary); Thermoreflectance thermography and infrared microscopy of AlGaN/GaN HEMTs, THERMINIC 2014, DOI 10.1109/THERMINIC.2014.6972538 (abstract only); MST product page on lock-in thermal analysis (vendor page, machine translated; no numbers).
Related pages in this vault: Mechanical and Package Stress, Wafer Geometry Gauge, X-Ray Diffractometer (XRD and HRXRD), Nanoindenter, X-Ray Topography, Electrical Stress, Diodes (PN, PIN, Schottky, Zener), Temperature Acceleration Models (Arrhenius and Eyring), Thermal and Electro-Thermal Simulation, Stylus Profiler, Wafer Curvature Stress Gauge, Pyrometers and Wafer Temperature Sensors.