Radiation stress is the damage that ionising and displacing particles do to a device. This page covers the three kinds that matter for electronics: total ionising dose, which charges oxides and interfaces; displacement damage, which moves atoms in the crystal; and single events, in which one particle upsets, latches up or destroys a device. Terrestrial soft errors from atmospheric neutrons and alpha particles are included, since they are single events. Heating by dissipated power is on the Thermal Stress page, breakdown of gate oxides and overstress on the Electrical Stress page, wear-out of metal lines on the Metal and Interconnect page, and the general statistics of lifetime on the Failure Rate and the Bathtub Curve page. The response of a particular technology, such as GaN or SiC, belongs to the device-specific folder, except where a source treats it as an example.
1. Why It Happens
- Trigger: Gamma rays, X-rays, electrons and protons that deposit dose in oxides (Oldham and McLean; Osheroff); protons, neutrons and electrons that displace atoms (Auden; Osheroff); a single heavy ion, proton, neutron or alpha particle that deposits charge in a sensitive node (O’Bryan et al.; Kato). On the ground the sources are neutrons from cosmic rays, alpha particles from package materials and thermal neutrons (Actel; Kato).
- Mechanism, total dose: Four steps act in an oxide: pairs form and part recombine at once; holes move through the oxide in a dispersive hop; holes that reach the interface are trapped in deep traps and anneal slowly; and interface traps form when hydrogen is released from Si-H bonds, by a two-stage process in which holes release protons that hop to the interface (Oldham and McLean). Trapped holes shift the threshold voltage negatively, and interface traps shift it negatively in p-channel and positively in n-channel devices (Poizat).
- Mechanism, rebound and dose rate: In an n-channel device the interface traps can offset the trapped holes after the irradiation; when the holes then anneal, a positive shift is left, in one example from below 1 to about 3.5 (Oldham and McLean). Bipolar devices show enhanced low dose rate sensitivity, a true dose-rate effect (Poizat; Kruckmeyer et al.), while for CMOS the apparent dose-rate effect comes from annealing during the different exposure times (Oldham and McLean).
- Mechanism, displacement damage: Displaced atoms act as recombination centres, which lower mobility and lifetime and raise the thermal generation rate; in a bipolar transistor the recombination current in the base and in the base-emitter depletion region rises, so the base current rises and the gain falls (Auden). Only about 0.1 per cent of the deposited energy goes into displacements (Poizat).
- Mechanism, single events: Charge collected at a node that exceeds the critical charge flips the stored state, and a rewrite corrects it (Kato). Destructive events are latch-up (a high-current state), burnout (positive feedback in the drain or collector) and gate rupture (Osheroff). In SiC power MOSFETs the cause of burnout is now seen as simultaneous high current and high field, not a parasitic bipolar turn-on, and the event ends thermally with sublimation of SiC (Grome and Ji).
- What sets the rate: Dose, dose rate for bipolar parts, bias during irradiation and oxide thickness for total dose (Oldham and McLean; Poizat); fluence, particle type and energy, and the gain and transition frequency for displacement damage (Auden; Baltateanu and Gheorghiu); the LET, the bias, the cross-section and the flux for single events (O’Bryan et al.; Osheroff); and altitude and latitude for the flux of atmospheric neutrons (Actel).
- Failure criterion: A reading outside the pre-irradiation limits (Kruckmeyer et al.), checked also after an anneal because of rebound (Oldham and McLean); a gain below the circuit limit; for single events an upset, a transient or a functional interrupt, and for latch-up a supply current monitored during the test (O’Bryan et al.).
2. Where to Look
- Location: Thick oxides, which are the field oxide, the isolation edges and the gate oxide of power devices (Oldham and McLean; Osheroff); bipolar linear circuits for low dose rate effects (Kruckmeyer et al.; Poizat); the base region of bipolar transistors for displacement damage (Auden); memory cells and flip-flops, mostly the n-channel drain of the high node (Kato); configuration cells of programmable logic (Actel); and the drift region of power MOSFETs and diodes for burnout (Grome and Ji).
- Signature: A shifted threshold voltage with more leakage current from oxide traps and slower timing from interface traps (Poizat); a field-oxide leakage that can rise by several orders of magnitude at 0 (Oldham and McLean); a gain that falls while the base current rises (Auden); single bit flips that go away on rewrite, and multi-bit upsets that a single-error-correcting code cannot fix (Kato); a high supply current that stays until the power is cycled for latch-up (Osheroff); and a permanent short for burnout or gate rupture (Osheroff).
- Confirm with: Irradiation with Co-60 or Cs-137 sources, electron accelerators or X-ray sources for dose (Osheroff); the low-dose-rate test at 10 (Kruckmeyer et al.); heavy-ion and proton beams, and a pulsed laser of 590 with a spot of about 1 (O’Bryan et al.); and a neutron beam such as LANSCE 30L for soft errors (PSU). A 100 anneal for 168 hours checks for rebound (Oldham and McLean).
- Look-alikes: A device that passes right after the irradiation and fails after the rebound anneal (Poizat; Oldham and McLean); an apparent dose-rate effect that is only annealing (Oldham and McLean); an upset that depends on the supply voltage, which can also come from other noise, for which the sources give no discrimination (my reading); and a latch-up that is triggered by an overvoltage and not by radiation, which the Electrical Stress page covers.
3. Prevention
- Design: Use error detection and correction and triple-module redundancy for memory, and configuration read-back at regular intervals and a board-level majority vote for SRAM-based FPGAs (Actel). Single-error-correcting codes do not correct multi-bit upsets (Kato), so the layout has to keep the bits of one word apart (my reading). Derate burnout-prone power devices, bearing in mind that derating is costly in on-resistance (Grome and Ji); use super-junction designs (Grome and Ji).
- Material and process: Thin gate oxides, since the shift scales as and thin oxides anneal (Oldham and McLean); hardened field oxide or trench isolation instead of LOCOS, whose methods are usually proprietary (Oldham and McLean); nitride encapsulation to suppress the latent buildup of interface traps (Oldham and McLean); removal of BPSG and the boron-10 that gave thermal-neutron fission, negligible from the 180 generation on (PSU); and Flash or antifuse programmable logic, which did not lose configuration under atmospheric neutrons (Actel).
- Operation: Reduce the time at the worst-case bias, use power cycling and derating (Osheroff), and keep the supply at its nominal value, because the lower supply gave more errors (PSU). For avionics, use system-level redundancy and an older technology, the 0.22 micron generation in the example (Actel).
- Screening and test: Total-dose tests to ESCC 22900, with at least 11 samples from each of two wafer lots for evaluation and 5 per condition at the least, and with the 10 test with a margin of two for bipolar parts (Poizat; Kruckmeyer et al.); the rebound anneal (Oldham and McLean); heavy-ion tests to an effective fluence of and proton tests (O’Bryan et al.); Weibull fits of the cross-section and Poisson bounds on the rate when events are few (Ladbury); and displacement-damage tests at reactors or proton accelerators (Osheroff).
Total Ionising Dose
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Electron-hole pairs made by an absorbed dose | |||
| Threshold-voltage shift from oxide and interface charge | |||
| Test duration and the ELDRS ratio |
Displacement Damage
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Gain and lifetime degradation from displacement damage | |||
| Displacement damage dose and equivalent fluence |
Single-Event Charge and Cross-Section
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Charge deposited by an ion and effective LET | |||
| Critical charge and upset condition | |||
| Weibull cross-section versus LET | |||
| Upper limit on the cross-section from a run without events |
Soft-Error Rates and Burnout
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Soft-error rate, FIT and MTBF | |||
| Burnout threshold as a fraction of the rated voltage |
Important Questions
Ques: How many electron-hole pairs does one rad make in silicon dioxide?
Oldham and McLean give about for a pair energy of 17 plus or minus 1 , and Poizat gives about with about 17 for the oxide, and with 3.6 for silicon. One rad is 100 , which is . With an assumed density of 2.2 and 17 this gives , and silicon at 2.33 gives (computed). The needs 17.6 , inside the stated error of 1 , and the difference of 4 per cent is small against the spread of the hole yield, which differs by more than an order of magnitude between particles at 1 . The value is more likely, because it follows directly from 17 and the usual density. Reference: Oldham and McLean, ‘Total Ionizing Dose Effects in MOS Oxides and Devices’ (year not stated, probably about 2003) (fetch-tool summary); Poizat (ESA), ‘Radiation environment and its effects in EEE components and hardness assurance for space applications’, CERN-ESA-SSC workshop slides, 9-10 May 2017 (fetch-tool summary; exponents garbled there and written as powers of ten).
Ques: How does the oxide thickness change the total-dose shift?
Oldham and McLean say the shift scales about as , and that the hole transit time grows with a power of about 4 of the thickness. Oxides thinner than about 10 anneal their trapped charge by tunnelling from both interfaces, so the net positive charge nearly vanishes. Poizat says only that thinner gate oxides are harder and that thick oxides are sensitive, with no equation. For the same trapped-charge density the shift of a 10 oxide is 0.01 of that of 100 , and for 3 it is 0.0009 (computed). The square law is therefore an upper bound for thin oxides, since the tunnelling lowers the shift further, so it is more likely to overstate than to understate the shift of a modern gate oxide. It does not apply to field oxide, which stays thick (my reading). Reference: Oldham and McLean, ‘Total Ionizing Dose Effects in MOS Oxides and Devices’ (year not stated, probably about 2003) (fetch-tool summary); Poizat (ESA), ‘Radiation environment and its effects in EEE components and hardness assurance for space applications’, CERN-ESA-SSC workshop slides, 9-10 May 2017 (fetch-tool summary; exponents garbled there and written as powers of ten).
Ques: Does the dose rate change the damage?
It depends on the technology. Oldham and McLean find that with matched annealing time there is no true dose-rate effect in CMOS over 11 orders of magnitude, and that apparent effects come from annealing during the different exposure times. Poizat states that enhanced low dose rate sensitivity is a true dose-rate effect and not a time effect, which applies to bipolar devices, with unbiased parts failing functionally at about 30 at low dose rate in his example. Kruckmeyer et al. define susceptibility by a ratio of median drift at low to high dose rate above 1.5. The two statements do not conflict if one is read for CMOS and the other for bipolar devices (my reading). For CMOS a high rate with the rebound anneal is more likely adequate, and for bipolar parts the low rate must be used. Reference: Oldham and McLean, ‘Total Ionizing Dose Effects in MOS Oxides and Devices’ (year not stated, probably about 2003) (fetch-tool summary); Poizat (ESA), ‘Radiation environment and its effects in EEE components and hardness assurance for space applications’, CERN-ESA-SSC workshop slides, 9-10 May 2017 (fetch-tool summary; exponents garbled there and written as powers of ten); Kruckmeyer, McGee, Trinh and Benedetto, ‘Low Dose Rate Test Results of National Semiconductor’s ELDRS-Free Bipolar Low Dropout (LDO) Regulator, LM2941 at Dose Rates of 1 and 10 mrad(Si)/s’, IEEE Radiation Effects Data Workshop, 2009 (fetch-tool summary).
Ques: Is the 10 mrad/s low-dose-rate test enough?
The MIL-STD-883G method uses 10 with a margin of two on drift (Kruckmeyer et al.), and 10 is the same as 36 , the lower edge of the second ESCC 22900 window (Poizat). Kruckmeyer et al. also tested a regulator at 1 and found that the drift differed from that at 10 by a fraction of the test guardband, but the part was not ELDRS-susceptible, and they note a possible effect between 10 and 30 . The duration is the cost: 100 at 36 takes 116 days, and 20 at 1 takes 231 days (computed). One part that is insensitive is weak evidence for the whole class, so 10 with the margin is the more likely adequate choice, and not a proof (my reading). Reference: Kruckmeyer, McGee, Trinh and Benedetto, ‘Low Dose Rate Test Results of National Semiconductor’s ELDRS-Free Bipolar Low Dropout (LDO) Regulator, LM2941 at Dose Rates of 1 and 10 mrad(Si)/s’, IEEE Radiation Effects Data Workshop, 2009 (fetch-tool summary); Poizat (ESA), ‘Radiation environment and its effects in EEE components and hardness assurance for space applications’, CERN-ESA-SSC workshop slides, 9-10 May 2017 (fetch-tool summary; exponents garbled there and written as powers of ten).
Ques: Is the displacement damage constant K one number?
No. Baltateanu and Gheorghiu give and say K is found from a graph and deviates at low fluence. Their table for 7 electrons has a gain of 79.0 before irradiation and 2.7 at , which gives K of (computed); the fetch summary quotes 1.2 to for fluences above , a range I could not check. Auden says only that the damage factor is a rate per unit of damage dose, and Tonigan shows that NIEL correlates neutron and proton results for three transistor types. K therefore depends on the particle, its energy, the device and the fluence range (my reading). The high-fluence value is the more likely to apply to a heavily damaged part, and it should not be moved to another device or particle. Reference: Baltateanu and Gheorghiu, ‘The Use of Linear Electron Accelerators in the Study of Semiconductor and Optoelectronic Device Behaviour Due to Irradiation’, EPAC 2002 (fetch-tool summary); Auden, ‘Basic Mechanisms: Displacement Damage’, Los Alamos National Laboratory radiation effects summer school, 7 June 2019 (LA-UR-19-25081) (fetch-tool summary of slides); A. M. Tonigan, ‘The theory and application of bipolar transistors as displacement damage sensors’, Vanderbilt University, 2017 (abstract only).
Ques: What charge does an ion deposit per unit of LET?
With 3.6 per pair (Kato) and an assumed silicon density of 2.33 , one deposits 10.4 , which is 64700 pairs per (computed). The value often quoted from memory is 10.8 , which needs a density of 2.43 (computed, background knowledge). The difference is 4 per cent. In reverse, 1 in silicon is 96 , but Grome and Ji give LET in for SiC, which has a larger pair energy, so that conversion cannot be reused (my reading). The LET also grows by with the angle of incidence (O’Bryan et al.). The 10.4 value is more likely correct for silicon, since it uses the real density, and the 4 per cent is small against the uncertainty of the sensitive depth. Reference: T. Kato, ‘An Experimental Study on Terrestrial Radiation-Induced Single Event Upsets in Planar and FinFET SRAMs’, Osaka University doctoral dissertation, January 2021 (fetch-tool summary); O’Bryan et al., ‘Compendium of Current Single Event Effects Results from NASA Goddard Space Flight Center and NASA Electronic Parts and Packaging Program’, IEEE NSREC Radiation Effects Data Workshop, July 2017 (fetch-tool summary); Grome and Ji, ‘A Brief Review of Single Event Burnout Failure Mechanisms and Design Tolerances of Silicon Carbide MOSFETs’, arXiv:2310.06184 (year not stated, 2023 or later) (fetch-tool summary).
Ques: Is single event burnout a parasitic bipolar effect or a thermal one?
Grome and Ji report that the older view is a parasitic bipolar turn-on as in silicon MOSFETs, while recent simulations and tests point to high current and high field together, with burnout in a simulation at 120 , far too fast for a bipolar turn-on. They also give conflicting temperature criteria: one study reports a maximum lattice temperature of 492 at burnout, well below sublimation, which the authors question, while others use 1500 or find failure at the contact above 1500 . The sublimation criterion with high current and high field is more likely, because the authors themselves doubt the low value, and many two-dimensional simulations are isothermal, which makes the temperature response unphysical. One simulation shows that fixing the thermal conductivity at 4.9 raises the threshold by about 700 . Reference: Grome and Ji, ‘A Brief Review of Single Event Burnout Failure Mechanisms and Design Tolerances of Silicon Carbide MOSFETs’, arXiv:2310.06184 (year not stated, 2023 or later) (fetch-tool summary).
Ques: Can burnout be avoided by derating the voltage?
The sources are split. Grome and Ji give burnout at 40 per cent of the rating or below for silicon MOSFETs, at 500 to 550 for a 1200 SiC MOSFET, and at 825 for a 3300 part, and they call derating impractical, because the 3300 part has a specific on-resistance of 10 against 3 for 1200 . Osheroff lists derating among the mitigations, without numbers. The fractions are 0.42 to 0.46 and 0.25, and a derated 650 for the 3300 part is 0.20 (computed). For unhardened parts a use voltage below 0.25 to 0.4 of the rating is more likely safe, but it wastes the part, so super-junction designs, which reached 1150 and 1750 , are the better answer (Grome and Ji). Reference: Grome and Ji, ‘A Brief Review of Single Event Burnout Failure Mechanisms and Design Tolerances of Silicon Carbide MOSFETs’, arXiv:2310.06184 (year not stated, 2023 or later) (fetch-tool summary); Osheroff, ‘Radiation Testing Tutorial’, NASA Goddard, Workshop on Power Electronics for Aerospace Applications (PEASA), 28 July 2026 (fetch-tool summary of slides).
Ques: How strongly does the soft-error rate depend on the supply voltage?
PSU report 15 errors in one hour at 3 against 2 at 5 for a memory rated at 5 , and conclude an exponential dependence. Two points cannot show that. The ratio is 7.5, or about 1.0 per volt if exponential (computed), but with 15 and 2 counts the one-sigma Poisson ranges are 11 to 20 and 0.7 to 4.6, so the ratio could lie between about 2.4 and 28 (computed, rough). Kato gives as about , which falls to 0.6 of its value from 5 to 3 for a fixed capacitance (computed). A strong rise at a lower supply is more likely, but the exponent is not fixed by this test, and the claim of an exponential law is not supported by two points. Reference: Vijaykrishnan, Irwin, Unlu, Degalahal and Cetiner, ‘Testing Neutron-Induced Soft Errors in Semiconductor Memories’, Penn State neutron beam group page (date not stated) (fetch-tool summary); T. Kato, ‘An Experimental Study on Terrestrial Radiation-Induced Single Event Upsets in Planar and FinFET SRAMs’, Osaka University doctoral dissertation, January 2021 (fetch-tool summary).
Ques: How much does altitude change the soft-error rate?
Actel says the neutron flux peaks near 60000 feet, Denver is more than 3 times New York, and the 30000 feet flux is about 40 times that of Denver. Its upset rates for one 0.13 micron device at Denver, 30000 and 60000 feet are , and per day, so the ratios are 44 and 4.5 (computed), which agrees with about 40 and with the source’s statement that 60000 feet is more than four times 30000 feet. With 3 for Denver over sea level the rate at 30000 feet is about 130 times the sea-level rate (computed, my reading). Kato’s sea-level flux of 13 for high-energy neutrons is the reference. The factor 3 is only a lower bound, so 130 is more likely too low than too high. Reference: Actel Corporation, ‘Effects of Neutrons on Programmable Logic’, white paper, December 2002 (fetch-tool summary); T. Kato, ‘An Experimental Study on Terrestrial Radiation-Induced Single Event Upsets in Planar and FinFET SRAMs’, Osaka University doctoral dissertation, January 2021 (fetch-tool summary).
Ques: Do thermal neutrons still matter for soft errors?
The sources differ. PSU say the thermal-neutron contribution through boron-10 fission became negligible from the 180 generation, after BPSG and boron-10 were removed, and that high-energy neutrons dominate advanced CMOS. Kato still lists a sea-level thermal flux of 6.5 against 13 for high-energy neutrons, half as much (computed), and Actel in 2002 names only cosmic-ray neutrons and alpha particles. A flux alone says nothing about the rate, which needs a cross-section, and none of the three gives one for thermal neutrons. For a process without BPSG the negligible contribution is more likely, but boron in other materials could still matter (my reading), and the sources do not tell which parts are affected. Reference: Vijaykrishnan, Irwin, Unlu, Degalahal and Cetiner, ‘Testing Neutron-Induced Soft Errors in Semiconductor Memories’, Penn State neutron beam group page (date not stated) (fetch-tool summary); T. Kato, ‘An Experimental Study on Terrestrial Radiation-Induced Single Event Upsets in Planar and FinFET SRAMs’, Osaka University doctoral dissertation, January 2021 (fetch-tool summary); Actel Corporation, ‘Effects of Neutrons on Programmable Logic’, white paper, December 2002 (fetch-tool summary).
Related pages in this vault: Electrical Stress, Thermal Stress, Metal and Interconnect, Static and Dynamic Random Access Memory (SRAM and DRAM), Floating Gate and Charge-Trap Flash Memory (NOR, NAND and 3D NAND), Failure Rate and the Bathtub Curve, Static Random Access Memory (SRAM), Silicon Power MOSFET, IGBT and Thyristors, Mechanical and Package Stress.