Power MOSFET (VDMOS, LDMOS, Superjunction, SiC, Ga2O3, Diamond)

1. Theory

• Definition: A power MOSFET is a MOSFET with a lightly doped drift region added between channel and drain so that it can block high voltage while switching large currents.
• Scope: This page covers five groups: vertical power MOSFETs (planar VDMOS, trench and shielded-gate), lateral LDMOS, superjunction MOSFETs, SiC MOSFETs and emerging $\mathrm{G}{\mathrm{a}}_2{\mathrm{O}}_3$ and diamond FETs; the IGBT has its own page.
• Drift region: A thick, lightly doped layer supports the blocking voltage; its resistance usually dominates $R_{on}$ at high voltage.
• Silicon limit: For a plain drift region, specific on-resistance rises roughly as $B{V}^{2.5}$, which makes Si unipolar devices impractical above a few hundred volts.
• Double-diffused channel: The channel length is set by the difference of two diffusions (P-body and ${\mathrm{N}}^{+}$ source), not by lithography.
• Unipolar conduction: Only majority carriers flow, so there is no stored minority charge and switching is fast; an intrinsic body diode exists between source and drain.

2. Working Principle

• VDMOS, trench and shielded-gate: Current flows from the surface channel vertically down through the drift region; trench gates remove the JFET constriction, and shielded gates cut the gate-drain charge.
• LDMOS: Current flows laterally; the RESURF principle (drift charge $\approx 10^{12}\mathrm{c}{\mathrm{m}}^{-2}$) lets the drift layer deplete vertically, raising lateral breakdown and allowing integration with CMOS.
• Superjunction: Alternating charge-balanced P and N pillars deplete sideways, giving a nearly uniform field so drift doping can rise, breaking the Si limit ($R_{on}$ roughly $\propto BV$ instead of $B{V}^{2.5}$).
• SiC MOSFET: The roughly tenfold higher critical field allows a thin, heavily doped drift layer; the poor SiC/$\mathrm{Si}{\mathrm{O}}_2$ interface lowers channel mobility, and the high oxide field and threshold drift are reliability concerns.
• $\mathrm{G}{\mathrm{a}}_2{\mathrm{O}}_3$ and diamond FETs: $\mathrm{G}{\mathrm{a}}_2{\mathrm{O}}_3$ has an even larger critical field but no p-type doping and poor heat conduction; diamond has extreme thermal conductivity but hard doping, often using a hydrogen-terminated surface channel.
• Switching: Gate charge and the Miller plateau set switching speed; losses split into conduction ($I^2{R}_{on}$) and switching (gate charge times frequency) parts.
• Avalanche ruggedness: Devices are rated to absorb unclamped inductive switching energy in avalanche.

3. Applications

• Low-voltage DC-DC conversion (trench and shielded-gate Si): CPU and GPU voltage regulators, battery management and synchronous rectification below about 200 V.
• RF power amplification (LDMOS): Broadcast, cellular base-station (sub-3 GHz) and industrial RF heating amplifiers.
• Mains-input power supplies (superjunction): PFC and flyback stages at 500–900 V in adapters, servers and lighting.
• EV and industrial power (SiC MOSFET): Traction inverters, on-board chargers, fast-charging stations and solar inverters at 650–3300 V.
• Ultra-high-voltage and high-temperature research ($\mathrm{G}{\mathrm{a}}_2{\mathrm{O}}_3$ and diamond): Still in development, aimed at kV-class and harsh-environment switching.

Vertical Power MOSFET (VDMOS, Trench and Shielded-Gate)

Name	Formula	Related Formulae	Variables/Constants
On-resistance components	$R_{on}=R_S+R_{CH}+R_A+R_J+R_D+R_{sub}$	$R_{on,sp}=R_{on}{A}_{cell}$	$R_S:sourcediffusionandcontactresistance$ $R_{CH}:channel(inversionlayer)resistance$ $R_A:accumulationlayerresistanceunderthegate$ $\begin{array}{r}{R}_J:JFETresistancebetweenthe\\ neighbouringp-bodyregions(zeroina\\ trenchdevice)\end{array}$ $R_D:driftregionresistance$ $R_{sub}:substrateresistance$ $R_{on,sp}:specificon-resistance$ $A_{cell}:activearea$
Channel resistance (specific)	$R_{CH,sp}=\frac{L_{ch}p}{{\mu }_{ni}{C}_{ox}\left(V_{GS}-V_{TH}\right)}$	$R_{CH,sp}\propto p\text{(smaller cell pitch lowers it)}$	$L_{ch}:channellengthsetbythebodydiffusion$ $\begin{array}{r}p:cellpitch,therepeatdistanceper\\ conductingchannel(acellwithtwo\\ channelsperperiodhasaneffective\\ pitchofhalfitswidth)\end{array}$ ${\mu }_{ni}:inversionlayermobility$ $C_{ox}:gateoxidecapacitanceperunitarea$ $V_{GS},V_{TH}:gatedriveandthresholdvoltage$
Ideal drift region resistance	$R_{on,sp}=\frac{4B{V}^2}{{\epsilon }_s{\mu }_n{E}_c^3}$	$N_D=\frac{{\epsilon }_s{E}_c^2}{2qBV},W_D=\frac{2BV}{E_c}$	$\begin{array}{r}BV:breakdownvoltageoftheblocking\\ junction(non-punch-through,parallel-plane)\end{array}$ ${\epsilon }_s:semiconductorpermittivity$ ${\mu }_n:bulkelectronmobilityofthedriftregion$ $\begin{array}{r}{E}_c:criticalelectricfieldforavalanche\\ breakdown\end{array}$ $N_D,W_D:driftdopingandthicknessatbreakdown$
Baliga figure of merit	$BFOM={\epsilon }_s{\mu }_n{E}_c^3$ $\frac{B{V}^2}{R_{on,sp}}=\frac{BFOM}{4}$	$R_{on,sp}(\text{Si, ideal})\approx 5.93\times 10^{-9}B{V}^{2.5}\mathrm{\Omega }\mathrm{c}{\mathrm{m}}^2(\text{older empirical fits give up to about }9\times 10^{-9})$	$\begin{array}{r}BFOM:materialfigureofmeritfor\\ conductionlossinaunipolarpower\\ switch(thesamedefinitionisusedon\\ theGaNPowerDiodeandSiCSchottky\\ Diodepages)\end{array}$ $BV:breakdownvoltageinvolts$ $R_{on,sp}:specificon-resistanceinohmc{m}^2$
Gate charge and Miller plateau	$V_{plateau}=V_{TH}+\frac{I_D}{g_m}$	$t_v=\frac{Q_{gd}}{I_g},I_g=\frac{V_{drive}-V_{plateau}}{R_g}$	$\begin{array}{r}{V}_{plateau}:gatevoltageduringthe\\ drainvoltagetransition(Millerplateau)\end{array}$ $g_m:transconductanceattheloadcurrent$ $Q_{gd}:gate-drain(Miller)charge$ $I_g:gatedrivecurrentduringtheplateau$ $V_{drive}:gatedriveroutputvoltage$ $R_g:totalgateresistance(driverplusinternal)$
Switching and conduction loss	$P_{cond}=I_{D,rms}^2{R}_{on}$ $P_{sw}\approx \frac{1}{2}{V}_{DS}{I}_D\left(t_r+t_f\right)f_s$	$P_g=Q_g{V}_{GS}{f}_s$	$\begin{array}{r}{P}_{cond}:conductionloss,with{R}_{on}at\\ theoperatingjunctiontemperature\end{array}$ $\begin{array}{r}{P}_{sw}:approximatehard-switchingloss\\ forlinearvoltageandcurrent\\ transitions\end{array}$ $t_r,t_f:currentriseandfalltimes$ $f_s:switchingfrequency$ $P_g:gatedriveloss$ $Q_g:totalgatecharge$
Switching figures of merit	$FO{M}_{Q_g}=R_{on}{Q}_g$ $FO{M}_{Q_{gd}}=R_{on}{Q}_{gd}$		$\begin{array}{r}FO{M}_{Q_g}:trade-offbetweenconduction\\ lossandgatedriveloss(loweris\\ better)\end{array}$ $\begin{array}{r}FO{M}_{Q_{gd}}:trade-offbetweenconduction\\ lossandtheMillerchargethatsets\\ theswitchingtime\end{array}$
Unclamped inductive switching (avalanche energy)	$E_{AS}=\frac{1}{2}L{I}_{AS}^2\frac{BV}{BV-V_{DD}}$		$\begin{array}{r}{E}_{AS}:single-pulseavalancheenergy\\ absorbedbythedevice\end{array}$ $L:loadinductance$ $I_{AS}:peakavalanchecurrent$ $V_{DD}:supplyvoltage$
Temperature dependence of on-resistance	$R_{on}(T)=R_{on}(T_0){\left(\frac{T}{T_0}\right)}^{\alpha }$	$T_j=T_c+P_{diss}{Z}_{th}$	$\begin{array}{r}\alpha :empiricalexponentsetbythe\\ phonon-limitedmobilityofthedrift\\ region(about2to2.7forSi)\end{array}$ $T_j,T_c:junctionandcasetemperature$ $Z_{th}:thermalimpedancefromjunctiontocase$

Lateral Double-Diffused MOSFET (LDMOS)

Name	Formula	Related Formulae	Variables/Constants
RESURF charge condition	$N_{epi}{t}_{epi}\approx 1\times 10^{12}\mathrm{c}{\mathrm{m}}^{-2}$	$N_{epi}{t}_{epi}\approx 2\times 10^{12}\mathrm{c}{\mathrm{m}}^{-2}\text{(double RESURF)}$	$\begin{array}{r}{N}_{epi}:dopingofthelightlydoped\\ n-typedriftlayerinap-substrate\\ device\end{array}$ $t_{epi}:driftlayerthickness$ $\begin{array}{r}\text{(the}\text{optimum}\text{integrated}\text{drift}\text{charge:}\\ \text{the}\text{layer}\text{then}\text{fully}\text{depletes}\text{before}\text{the}\\ \text{junction}\text{reaches}\text{critical}\text{field.}\text{Both}\text{a}\\ \text{higher}\text{and}\text{a}\text{lower}\text{charge}\text{reduce}BV\text{)}\end{array}$
Ideal lateral breakdown voltage	$BV\approx E_c{L}_d$		$\begin{array}{r}BV:breakdownvoltageforauniform\\ fieldalongthedriftregion(ideal\\ RESURFprofile)\end{array}$ $E_c:criticalfield$ $L_d:driftregionlength$
Drift region specific resistance	$R_{on,sp}=\frac{L_d^2}{q{\mu }_n{N}_{epi}{t}_{epi}}$	$R_{sh}=\frac{1}{q{\mu }_n{N}_{epi}{t}_{epi}}$	$\begin{array}{r}{R}_{on,sp}:driftresistancetimesthe\\ areaofthedriftregion(widthtimes\\ length)\end{array}$ $R_{sh}:sheetresistanceofthedriftlayer$ ${\mu }_n:electronmobilityinthedriftlayer$

Superjunction MOSFET

Name	Formula	Related Formulae	Variables/Constants
Charge balance	$N_D{W}_n=N_A{W}_p$ $\Delta Q=\frac{N_D{W}_n-N_A{W}_p}{N_D{W}_n}$		$N_D,N_A:dopingofthen-typeandp-typepillars$ $W_n,W_p:widthsofthen-typeandp-typepillars$ $\begin{array}{r}\Delta Q:fractionalchargeimbalance,\\ zeroforanidealdevice\end{array}$
Pillar doping limit (ideal)	$NW\le \frac{2{\epsilon }_s{E}_c}{q}$	$E_{lat,max}=\frac{qNW}{2{\epsilon }_s}\le E_c$	$\begin{array}{r}N,W:dopingandwidthofabalanced\\ pillar(N=N_D=N_A,W=W_n=W_p)\end{array}$ $\begin{array}{r}{E}_{lat,max}:peaklateralfieldatthe\\ pillarboundaryafterthepillarsare\\ fullydepletedsideways\end{array}$ $\begin{array}{r}{E}_c:criticalfield,evaluatedatthe\\ pillardoping\end{array}$ $\begin{array}{r}\text{(W}\text{is}\text{the}\text{full}\text{pillar}\text{width,}\text{depleted}\\ \text{from}\text{both}\text{sides;}\text{practical}\text{designs}\text{use}\text{a}\\ \text{lower}NW\text{because}\text{the}\text{lateral}\text{and}\\ \text{vertical}\text{fields}\text{add)}\end{array}$
Ideal breakdown voltage	$BV=E_c{t}_d$		$\begin{array}{r}{t}_d:thicknessofthepillar(drift)\\ region,whichisdepletedverticallywith\\ anearlyuniformfield\end{array}$ $E_c:criticalfield$
Idealized specific on-resistance (lower bound)	$R_{on,sp}=\frac{WBV}{{\mu }_n{\epsilon }_s{E}_c^2}$	$R_{on,sp}\propto BV\text{(compare }B{V}^{2.5}\text{for a plain drift region)}$	$W:pillarwidth$ $BV:breakdownvoltageinvolts$ ${\mu }_n:electronmobilityinthen-pillar$ $\begin{array}{r}{R}_{on,sp}:idealizedlowerboundforan\\ n-pillarthatfillshalfofthearea,\\ isdopedatthelimitaboveandseesa\\ uniformverticalfield{E}_c(published\\ optimizeddesignshavealarger\\ prefactor,seeFujihira)\end{array}$

Silicon Carbide MOSFET

Name	Formula	Related Formulae	Variables/Constants
Specific on-resistance split	$R_{on,sp}=R_{CH,sp}+R_{drift,sp}+R_{other}$	$R_{CH,sp}=\frac{L_{ch}p}{{\mu }_{ni}{C}_{ox}\left(V_{GS}-V_{TH}\right)}$	$\begin{array}{r}{R}_{CH,sp}:channelresistancewhich\\ dominatesatlowvoltagebecause{\mu }_{ni}\\ isfarbelowthebulkmobility\end{array}$ $\begin{array}{r}{R}_{drift,sp}:driftregionresistance,\\ givenbytheidealexpressioninthe\\ verticalpowerMOSFETtable\end{array}$ $\begin{array}{r}{R}_{other}:source,JFET,substrateand\\ contactresistances\end{array}$ $\begin{array}{r}{\mu }_{ni}:inversionlayermobilityofthe\\ SiC/Si{O}_{2}interface\end{array}$ $\begin{array}{r}p:cellpitch,therepeatdistanceper\\ conductingchannel\end{array}$ $L_{ch}:channellength$ $C_{ox}:gateoxidecapacitanceperunitarea$ $V_{GS},V_{TH}:gatedriveandthresholdvoltage$
Channel mobility	$\frac{1}{{\mu }_{ni}}=\frac{1}{{\mu }_{ph}}+\frac{1}{{\mu }_C}+\frac{1}{{\mu }_{sr}}$		${\mu }_{ph}:phononlimitedmobility$ $\begin{array}{r}{\mu }_C:Coulombscatteringmobilityfrom\\ interfaceandoxidecharge(largeinSiC\\ becauseofthehighinterfacetrap\\ density)\end{array}$ ${\mu }_{sr}:surfaceroughnesslimitedmobility$
Oxide field in the blocking state	$E_{ox}=\frac{{\epsilon }_{SiC}}{{\epsilon }_{ox}}{E}_s$	${\epsilon }_{SiC}{E}_s={\epsilon }_{ox}{E}_{ox}\text{(continuity of the displacement field)}$	$\begin{array}{r}{E}_{ox}:fieldinthegateoxideover\\ theJFETregion,about2.5timesthe\\ semiconductorfieldsince\\ {\epsilon }_{SiC}/{\epsilon }_{ox}\approx 2.5\end{array}$ $\begin{array}{r}{E}_s:fieldinthesemiconductoratthe\\ oxideinterface\end{array}$
Fowler-Nordheim tunneling through the gate oxide	$J_{FN}=\frac{q^2{E}_{ox}^2}{16{\pi }^2\hslash {\varphi }_B}\exp \left[-\frac{4\sqrt{2m_{ox}^{\ast }}{\left(q{\varphi }_B\right)}^{3/2}}{3q\hslash E_{ox}}\right]$		$J_{FN}:tunnelingcurrentdensitythroughtheoxide$ $\begin{array}{r}{\varphi }_B:barrierheightatthe\\ semiconductor/oxideinterfaceinvolts\\ (smallerforSiC/Si{O}_{2}thanforSi/Si{O}_2)\end{array}$ $m_{ox}^{\ast }:electroneffectivemassintheoxide$ $E_{ox}:oxidefield$
Threshold voltage instability	$\Delta V_{TH}=-\frac{\Delta Q_{ox}+\Delta Q_{it}}{C_{ox}}$	$\Delta Q_{it}=q\int D_{it}(E)\Delta f(E)dE$	$\begin{array}{r}\Delta V_{TH}:thresholdshiftcausedby\\ oxideandinterfacechargetrappingunder\\ gatebiasandtemperature\end{array}$ $\begin{array}{r}\Delta Q_{ox},\Delta Q_{it}:changein\\ oxideandinterfacetrapchargeperunit\\ area\end{array}$ $\begin{array}{r}{D}_{it}:interfacetrapdensityperunit\\ areaandenergy\end{array}$ $\Delta f:changeintrapoccupancy$

Emerging Wide-Bandgap FETs (Ga2O3 and Diamond)

Name	Formula	Related Formulae	Variables/Constants
Johnson figure of merit	$JFOM=\frac{E_c{v}_{sat}}{2\pi }$		$\begin{array}{r}JFOM:power-frequencylimitofa\\ high-frequencypowertransistor\end{array}$ $v_{sat}:saturatedcarrierdriftvelocity$
Baliga high-frequency figure of merit	$BHFFOM=\mu E_c^2$		$\begin{array}{r}BHFFOM:figureofmeritforswitching\\ lossathighfrequency,inwhichthe\\ gatecapacitancedominates\end{array}$ $\mu :carriermobilityofthechannel$
Keyes figure of merit	$KFOM=\kappa \sqrt{\frac{c{v}_{sat}}{4\pi {\epsilon }_r}}$		$\begin{array}{r}KFOM:figureofmeritforthermallimits\\ toswitchingspeed\end{array}$ $\kappa :thermalconductivity$ $c:speedoflight$ $\begin{array}{r}{\epsilon }_r:relativepermittivity(Keyes\\ form,writteninGaussianunits)\end{array}$
Self-heating	$\Delta T=P_{diss}{R}_{th}$	$R_{th}\approx \frac{t}{\kappa A}\text{(one-dimensional conduction)}$	$\Delta T:junctiontemperaturerise$ $P_{diss}:dissipatedpower$ $R_{th}:thermalresistancefromchanneltoheatsink$ $t,A:thicknessandareaoftheconductionpath$
Hydrogen-terminated diamond FET sheet resistance	$R_{sh}=\frac{1}{q{p}_s{\mu }_p}$	$I_D=\frac{Z}{L}{\mu }_p{C}_g\left(V_{GS}-V_{TH}\right)V_{DS}\text{(linear region)}$	$\begin{array}{r}{R}_{sh}:sheetresistanceofthe\\ two-dimensionalholegasformedby\\ surfacetransferdoping\end{array}$ $p_s:sheetholedensity$ ${\mu }_p:holemobility$ $C_g:gatecapacitanceperunitarea$

Important Questions

Ques: Why does the specific on-resistance of a silicon power MOSFET grow as roughly $B{V}^{2.5}$ and how does a superjunction break this?

For a plain drift region, raising the blocking voltage needs both a thicker and a more lightly doped layer, since $W_D=2BV/E_c$ and $N_D={\epsilon }_s{E}_c^2/(2qBV)$. The resistance is $W_D/(q{\mu }_n{N}_D)=4B{V}^2/({\epsilon }_s{\mu }_n{E}_c^3)$, which scales as $B{V}^2$ if the critical field is held constant. The critical field is not constant: it falls as the doping is lowered ($E_c\propto N^{1/8}$ and $BV\propto N^{-3/4}$, so $E_c^3\propto B{V}^{-1/2}$), and this raises the exponent from 2 to about 2.5. A superjunction replaces the single lightly doped layer by alternating n and p pillars, which deplete sideways into each other. With balanced charge the vertical field is nearly uniform, so the pillar doping can be raised far above the plain-drift value without lowering breakdown, and the ideal resistance grows linearly with $BV$ at fixed pillar width. Reference: B.J. Baliga, Fundamentals of Power Semiconductor Devices, Springer, 2008; T. Fujihira, “Theory of Semiconductor Superjunction Devices,” Jpn. J. Appl. Phys. 36, 6254 (1997).

Ques: Why is there no JFET resistance in a trench MOSFET?

In a planar double-diffused device the p-body regions of neighbouring cells squeeze the current into a narrow neck between them, giving the JFET resistance $R_J$. In a trench device the gate sits in a vertical trench, the channel runs along the trench wall, and current flows straight down into the drift region without passing a constriction, so $R_J=0$. The cell pitch can also be reduced, which lowers $R_{CH,sp}\propto p$. The cost is a larger gate-drain capacitance, because the trench bottom faces the drift region; shielded-gate designs place a source-connected electrode under the gate to reduce $Q_{gd}$ and let the drift doping be increased. Reference: B.J. Baliga, Fundamentals of Power Semiconductor Devices, Springer, 2008.

Ques: What does the RESURF principle do in a lateral device?

In a lateral high-voltage transistor the drift layer sits on a substrate junction of the opposite type, and the vertical and lateral depletion fields add near the surface, which makes the device break down at a low voltage. When the integrated drift charge is kept near $10^{12}\mathrm{c}{\mathrm{m}}^{-2}$, the thin layer depletes fully from the substrate junction before the lateral field reaches critical, so the surface field is reduced and made nearly uniform. Breakdown then approaches $E_c{L}_d$, much higher than for an unreduced surface field. Reference: J.A. Appels and H.M.J. Vaes, “High voltage thin layer devices (RESURF devices),” IEDM Tech. Dig., 238 (1979); B.J. Baliga, Fundamentals of Power Semiconductor Devices, Springer, 2008.

Ques: Why is the channel mobility of SiC MOSFETs much lower than the bulk mobility?

Oxidising SiC leaves carbon-related defects at the interface and a high density of interface traps near the conduction band edge. These traps capture inversion electrons, which reduces the free carrier density and adds Coulomb scattering, so ${\mu }_{ni}$ falls to tens of $\mathrm{c}{\mathrm{m}}^2/V\mathrm{s}$ against several hundred in the bulk. The channel resistance $R_{CH,sp}$ then dominates the on-resistance at blocking voltages below a few kilovolts, and it is the main reason why the SiC MOSFET is limited by its gate oxide rather than by its drift region. Nitridation anneals in NO or N${}_2$O reduce the trap density and raise the mobility. Reference: T. Kimoto and J.A. Cooper, Fundamentals of Silicon Carbide Technology, Wiley, 2014.

Ques: Why do Ga${}_2$O${}_3$ and diamond power FETs need different design approaches?

$\beta$-Ga${}_2$O${}_3$ has a very large bandgap and a high critical field, but it has no usable p-type doping and a low thermal conductivity, so it supports only unipolar devices and suffers from strong self-heating, $\Delta T=P_{diss}{R}_{th}$, that must be handled by thin substrates and heat spreading. Diamond has an extremely high thermal conductivity, so self-heating is small, but doping is difficult and carriers freeze out: n-type doping is hard, and the p-type dopant boron is deep. Hydrogen-terminated diamond FETs therefore use a surface two-dimensional hole gas formed by transfer doping rather than a doped channel. Reference: B.J. Baliga, Wide Bandgap Semiconductor Power Devices, Woodhead Publishing, 2019; S.J. Pearton et al., “A review of Ga${}_2$O${}_3$ materials, processing, and devices,” Appl. Phys. Rev. 5, 011301 (2018).

Related pages in this vault: Insulated Gate Bipolar Transistor (IGBT), Junction Field Effect Transistor (JFET), Static Induction Transistor (SIT), Metal Semiconductor Field Effect Transistor (MESFET), SiC Schottky Diode, GaN HEMT, Power Device Compact Models, SiC and Ga2O3 Power Devices, Silicon Power MOSFET, IGBT and Thyristors.