Junction Field Effect Transistor (JFET)

1. Theory

Definition: A junction field-effect transistor (JFET) is a unipolar transistor in which reverse-biased PN gate junctions on either side of a doped channel control its conducting thickness.
Reference device: This page uses an n-channel JFET with symmetric abrupt $P^{+}$ -N gates on both sides of a channel of full thickness $2 a$ ; a p-channel JFET follows with all doping and polarities swapped.
Bulk channel: Current flows through the neutral interior of the doped channel, away from any surface or oxide interface.
Depletion-mode device: The channel conducts at $V_{GS} = 0$ and is turned off by making the gate more negative, down to the cut-off voltage $V_{GS (o f f)}$ .
Pinch-off voltage: $V_{P 0} = q N_{D} a^{2} /2 ε_{s}$ is the junction voltage at which the two gate depletion regions just meet across the channel.
High input resistance: The gate is a reverse-biased junction, so only leakage flows (about $1 0^{9}$ to $1 0^{12} Ω$ ), though less than a MOSFET’s insulated gate.
MESFET relation: Replacing the PN gate with a Schottky gate gives the MESFET, which uses the same equations.

2. Working Principle

Gate control: Raising the gate reverse bias widens the depletion regions, narrows the channel and lowers its conductance.
Linear region: At small $V_{D S}$ the channel acts as a voltage-controlled resistor.
Pinch-off and saturation: The depletion is widest at the drain end; when $V_{D S} = V_{GS} - V_{GS (o f f)}$ the channel pinches off there and the current saturates.
Square-law approximation: In saturation, $I_{D} \approx I_{D S S} (1 - V_{GS} / V_{GS (o f f)})^{2}$ , a fit to the exact Shockley expression.
Gate must stay reverse biased: If $V_{GS}$ approaches $V_{bi}$ the gate junction conducts and the high input resistance is lost.
Low $1/ f$ noise: The buried bulk channel avoids interface traps, giving much lower flicker noise than a MOSFET.

3. Applications

Low-noise, high-impedance front ends: Electret microphone capsules, piezoelectric and charge amplifiers, and radiation-detector preamplifiers.
JFET-input op-amps and instrumentation amplifiers: Low input current with low low-frequency noise.
Current-regulator diodes: A JFET with gate tied to source acts as a simple two-terminal constant-current source.
SiC power JFETs: Normally-on, very low on-resistance switches for solid-state circuit breakers and cascode power stages.

Name	Formula	Related Formulae	Variables/Constants
Gate depletion width	$W (y) = \frac{2 ε _{s} [ V _{bi} - V _{GS} + V ( y ) ]}{q N _{D}}$	$(see PN Junction Diode page; one-sided junction)$	$W (y) : d e pl e t i o n w i d t h a t p os i t i o n y a l o n g t h e c hann e l$ $V (y) : c hann e l p o t e n t ia l r e l a t i v e t o t h e so u r ce (0 a t t h e so u r ce, V_{D S} a t t h e d r ain)$ $V_{bi} : g a t e j u n c t i o n b u i l t - in p o t e n t ia l$ $N_{D} : c hann e l d o n or co n ce n t r a t i o n$
Internal pinch-off voltage	$V_{P 0} = \frac{q N _{D} a ^{2}}{2 ε _{s}}$	$W = a at V_{bi} - V_{GS} + V (y) = V_{P 0}$	$V_{P 0} : t o t a l j u n c t i o n v o l t a g e a t w hi c h t h e tw o d e pl e t i o n r e g i o n s j u s t m ee t a cr oss t h e c hann e l$ $a : c hann e l ha l f - t hi c k n ess$
Gate cutoff (threshold) voltage	$V_{GS (o f f)} = V_{bi} - V_{P 0}$	$V_{GS (o f f)} < 0 for a depletion-mode device$	$V_{GS (o f f)} : g a t e - so u r ce v o l t a g e a t w hi c h t h e c hann e l i s f u l l y d e pl e t e d an d t h e d r ain c u r r e n t g oes t o z er o$
Fully open channel conductance	$G_{0} = \frac{2 q μ _{n} N _{D} a Z}{L}$	$σ = q μ_{n} N_{D} (see Basic Semiconductor Equations page)$	$G_{0} : c hann e l co n d u c t an ce w i t h n o d e pl e t i o n$ $μ_{n} : e l ec t r o n m o bi l i t y$ $Z, L : c hann e l w i d t h an d l e n g t h$
Linear-region drain current (Shockley)	$I_{D} = G_{0} {V_{D S} - \frac{2}{3} \frac{( V _{D S} + V _{bi} - V _{GS} ) ^{3/2} - ( V _{bi} - V _{GS} ) ^{3/2}}{V _{P 0}^{1/2}}}$	$g_{d} = \frac{\partial I _{D}}{\partial V _{D S}}_{V_{D S} \to 0} \to G_{0} [1 - \frac{V _{bi} - V _{GS}}{V _{P 0}}]$	$I_{D} : d r ain c u r r e n t$ $V_{D S}, V_{GS} : d r ain - so u r ce an d g a t e - so u r ce v o l t a g es$ $g_{d} : d r ain (c hann e l) co n d u c t an ce a t s ma l l V_{D S}$
Saturation drain voltage	$V_{D s a t} = V_{P 0} - (V_{bi} - V_{GS}) = V_{GS} - V_{GS (o f f)}$		$V_{D s a t} : d r ain v o l t a g e a t w hi c h t h e c hann e l p in c h es o f f a t t h e d r ain e n d$
Saturation drain current (Shockley)	$I_{D s a t} = G_{0} V_{P 0} [\frac{1}{3} - \frac{V _{bi} - V _{GS}}{V _{P 0}} + \frac{2}{3} (\frac{V _{bi} - V _{GS}}{V _{P 0}})^{3/2}]$	$I_{D s a t} (V_{GS} = V_{bi}) = \frac{G _{0} V _{P 0}}{3}$	$I_{D s a t} : d r ain c u r r e n t in t h e s a t u r a t i o n r e g i o n$ $(zero when V_{GS} = V_{GS (o f f)})$
Square-law approximation	$I_{D} \approx I_{D S S} (1 - \frac{V _{GS}}{V _{GS (o f f)}})^{2}$	$I_{D S S} = I_{D s a t} (V_{GS} = 0)$	$I_{D S S} : s a t u r a t i o n d r ain c u r r e n t a t z er o g a t e bia s$ $(empirical fit commonly used in circuit design; the exact form above is preferred for device physics)$
Transconductance (saturation)	$g_{m} = G_{0} [1 - \frac{V _{bi} - V _{GS}}{V _{P 0}}]$	$g_{m} \approx \frac{2 I _{D S S}}{∣ V _{GS (o f f)} ∣} (1 - \frac{V _{GS}}{V _{GS (o f f)}})$	$g_{m} : t r an sco n d u c t an ce \partial I_{D} / \partial V_{GS}$
Output conductance (channel-length modulation)	$g_{d s} = λ I_{D}$	$r_{o} = \frac{1}{g _{d s}} = \frac{1}{λ I _{D}}$	$g_{d s} : s ma l l - s i g na l o u tp u t co n d u c t an ce in s a t u r a t i o n$ $λ : c hann e l - l e n g t h m o d u l a t i o n p a r am e t er, d escr ibin g t h e s h or t e nin g o f t h e u n p in c h e d c hann e l a s V_{D S} in cr e a ses$
Cutoff frequency	$f_{T} = \frac{g _{m}}{2 π C _{G}} = \frac{q μ _{n} N _{D} a ^{2}}{2 π ε _{s} L ^{2}} = \frac{μ _{n} V _{P 0}}{π L ^{2}}$	$g_{m, ma x} = G_{0}, C_{G} \approx \frac{2 ε _{s} Z L}{a}$	$f_{T} : f r e q u e n cy a t w hi c h t h e s h or t - c i r c u i t c u r r e n t g ain f a l l s t o u ni t y$ $C_{G} : t o t a l g a t e c a p a c i t an ce (b o t h g a t es)$ $(neglects velocity saturation, which limits short channel devices)$

Important Questions

Ques: What does “pinch-off” mean, and why does drain current saturate instead of going to zero?

Because the drain end of the channel is at a higher potential than the source end, the reverse bias on the gate junction (and therefore the depletion width) is largest at the drain. When $V_{D S}$ reaches $V_{D s a t}$ , the depletion regions meet at the drain end and the channel there is pinched to zero thickness. Current does not stop, because carriers arriving at the pinched point are swept across the narrow high-field depletion region to the drain. Beyond $V_{D s a t}$ the extra drain voltage is dropped across this depleted region, while the voltage across the conducting part of the channel stays fixed at about $V_{D s a t}$ , so the current stays nearly constant. Only a gate voltage that makes $V_{D s a t} = 0$ , i.e. $V_{GS} = V_{GS (o f f)}$ , shuts the current off entirely. The small remaining slope is the channel-length modulation described by $λ$ . Reference: W. Shockley, “A unipolar field-effect transistor,” Proc. IRE 40, 1365 (1952); S.M. Sze and Kwok K. Ng, Physics of Semiconductor Devices, 3rd ed., Wiley, 2007.

Ques: Why does a JFET have such a high input resistance, and what limits it?

The gate is a reverse-biased p-n junction, so the only gate current is the junction’s small reverse saturation or leakage current (see the PN Junction Diode page), which gives input resistances of typically $1 0^{9}$ to $1 0^{12} Ω$ or higher. This is lower than a MOSFET, whose insulating oxide blocks DC gate current entirely. The limit is that the gate must stay reverse biased: if $V_{GS}$ rises to near $V_{bi}$ the junction conducts, the input resistance collapses, and the gate current is no longer negligible. Leakage also rises with temperature, since the reverse saturation current scales with $n_{i}^{2}$ . Reference: S.M. Sze and Kwok K. Ng, Physics of Semiconductor Devices, 3rd ed., Wiley, 2007.

Ques: How should the exact Shockley expression be used versus the square-law approximation?

The Shockley equations follow from the physical gradual-channel model and relate current directly to device parameters ( $N_{D}$ , $a$ , $μ_{n}$ , $Z / L$ ). In saturation, they give a function that is close to, but not exactly, a parabola in $V_{GS}$ . The square-law form $I_{D} \approx I_{D S S} (1 - V_{GS} / V_{GS (o f f)})^{2}$ is an empirical fit that needs only the two datasheet numbers $I_{D S S}$ and $V_{GS (o f f)}$ , and it matches the exact curve well enough for most circuit design. Use the exact expression when you want to predict behavior from doping and geometry, or to see how $g_{m}$ depends on $V_{bi}$ and $V_{P 0}$ ; use the square-law form when working from measured parameters. Reference: S.M. Sze and Kwok K. Ng, Physics of Semiconductor Devices, 3rd ed., Wiley, 2007.

Ques: Why are JFETs used for low-noise front ends?

Conduction takes place in the bulk of the channel, away from any surface, whereas in a MOSFET the current flows in a thin inversion layer right at the oxide interface, where traps and surface states generate substantial flicker (1/f) noise. A JFET’s buried channel therefore has lower low-frequency noise, together with its very high input resistance and low gate leakage current, which makes it a common choice for low-noise, high-impedance amplifier inputs such as those for microphones and sensors. Reference: S.M. Sze and Kwok K. Ng, Physics of Semiconductor Devices, 3rd ed., Wiley, 2007.

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