Static Induction Transistor (SIT)

1. Theory

Definition: A static induction transistor (SIT) is a vertical, short-channel, lightly doped JFET (or Schottky-gate MESFET) in which both gate and drain control a potential barrier in the channel, like the grid and plate of a vacuum triode.
Saddle-point barrier: Electrons must cross a potential barrier between closely spaced gate regions; its height is set by both gate and drain voltages.
Drain penetration: The channel is too short and narrow for the gate to screen it from the drain, so the drain field lowers the barrier directly.
Amplification factor: $μ = α_{G} / α_{D}$ measures how much more strongly the gate controls the barrier than the drain does ( $μ = g_{m} r_{d}$ ).
Normally on or off: If $V_{P 0} < V_{bi}$ the built-in depletion alone pinches off the channel (normally off); otherwise the device is normally on.

2. Working Principle

Barrier-controlled conduction: At low current, drain current rises exponentially as gate and drain voltages lower the barrier (thermionic passage over it).
Triode-like characteristics: The current keeps rising with $V_{D S}$ instead of saturating, following an effective control voltage $V_{e f f} = V_{GS} + V_{D S} / μ$ .
Space-charge-limited region: At higher current, the channel and drift region carry space-charge-limited current ( $I_{D} \propto V_{e f f}^{m}$ with $1 < m < 2$ ).
Voltage blocking: A negative gate bias raises the barrier so the device blocks about $μ (V_{T} - V_{GS})$ of drain voltage, up to gate-drain avalanche.
Bipolar mode: Forward-biasing the gate injects minority carriers that lower on-resistance by conductivity modulation, at the cost of slower switching.
Speed limit: The interleaved gate structure gives a large input capacitance, which limits $f_{T}$ .

3. Applications

Current status: Largely displaced by power MOSFETs and IGBTs in power electronics and by LDMOS and GaN HEMTs in RF.
Remaining niches: Some SiC SITs for pulsed power and high-power RF or induction heating.
Historical role: Linear high-fidelity audio output stages, high-frequency induction heating and broadcast RF transmitters.

Name	Formula	Related Formulae	Variables/Constants
Normally-on / normally-off criterion	$V_{P 0} < V_{bi} : normally off; V_{P 0} > V_{bi} : normally on$	$V_{P 0} = \frac{q N _{D} a ^{2}}{2 ε _{s}} (see Junction Field-Effect Transistor page)$	$V_{P 0} : in t er na l p in c h o f f v o l t a g e o f t h e c hann e l$ $V_{bi} : g a t e j u n c t i o n b u i l t - in p o t e n t ia l$ $a : c hann e l ha l f - w i d t h b e tw ee n g a t e r e g i o n s$ $(a narrow, lightly doped channel is fully depleted by the built-in potential alone)$
Saddle-point barrier height	$ϕ_{B} = ϕ_{B 0} - α_{G} V_{GS} - α_{D} V_{D S}$	$V_{GS} < 0 raises the barrier; V_{D S} > 0 lowers it$	$ϕ_{B} : h e i g h t o f t h e p o t e n t ia l ba r r i er (s a dd l e p o in t) t ha t e l ec t r o n s m u s t cr oss b e tw ee n so u r ce an d d r ain$ $ϕ_{B 0} : ba r r i er h e i g h t a t z er o bia s$ $α_{G}, α_{D} : co u pl in g coe f f i c i e n t s o f t h e g a t e an d t h e d r ain t o t h e s a dd l e p o in t$
Barrier-controlled drain current	$I_{D} = I_{S 0} exp [\frac{q ( α _{G} V _{GS} + α _{D} V _{D S} )}{k _{B} T}]$	$I_{S 0} = A A^{*} T^{2} exp (- \frac{q ϕ _{B 0}}{k _{B} T}) (see Schottky Diode page)$	$I_{D} : d r ain c u r r e n t, se t b y t h er mi o ni c p a ss a g e o v er t h e ba r r i er$ $A : e f f ec t i v e co n d u c t in g a r e a$ $A^{*} : e f f ec t i v e R i c ha r d so n co n s t an t$ $(exponential, subthreshold-like region at low current)$ $k_{B} : B o l t z mann co n s t an t$
Voltage amplification factor	$μ = \frac{α _{G}}{α _{D}} = - (\frac{\partial V _{D S}}{\partial V _{GS}})_{I_{D}}$	$μ = g_{m} r_{d}, r_{d} = (\frac{\partial V _{D S}}{\partial I _{D}})_{V_{GS}}$	$μ : am pl i f i c a t i o n f a c t or (t h e g a t e i s μ t im es m or e e f f ec t i v e t han t h e d r ain a t co n t r o l l in g t h e ba r r i er)$ $g_{m} : t r an sco n d u c t an ce$ $r_{d} : d i f f er e n t ia l d r ain (o u tp u t) r es i s t an ce$
Effective control voltage	$V_{e f f} = V_{GS} + \frac{V _{D S}}{μ}$	$I_{D} = I_{S 0} exp [\frac{q α _{G} V _{e f f}}{k _{B} T}]$	$V_{e f f} : s in g l e v o l t a g e co mbinin g t h e g a t e an d sc a l e d d r ain v o l t a g es (s am e r o l e a s V_{g} + V_{p} / μ in a v a c uu m t r i o d e)$ $k_{B} : B o l t z mann co n s t an t$
Triode-like region (empirical)	$I_{D} \approx K (V_{e f f} - V_{T})^{m}, 1 < m < 2$	$(space-charge-limited conduction in the channel/drift region)$	$K, m : e m p i r i c a l co n s t an t s f i tt e d t o m e a s u r e d c ha r a c t er i s t i cs$ $V_{T} : t h r es h o l d v a l u e o f t h e e f f ec t i v e co n t r o l v o l t a g e$ $(no pinchoff saturation: current keeps rising with V_{D S})$
Blocking gain and blocking voltage	$V_{D S, b l oc k} \approx μ (V_{T} - V_{GS})$	$blocking gain = \frac{V _{D S, b l oc k}}{∣ V _{GS} ∣} \to μ$	$V_{D S, b l oc k} : d r ain v o l t a g e t ha t t h e S I T c an h o l d o f f w i t h g a t e bia s V_{GS} (V_{GS} < V_{T})$ $(limited in practice by gate-drain avalanche breakdown, see Avalanche Diode page)$
Specific on-resistance (unipolar limit)	$R_{o n, s p} \approx \frac{W _{d r i f t}}{q μ _{n} N _{D}}$	$R_{o n, s p} = \frac{4 B V ^{2}}{ε _{s} μ _{n} E _{cr i t}^{3}} (see GaN Power Diode page)$	$R_{o n, s p} : a r e a - n or ma l i z e d o n - r es i s t an ce o f t h e u ni p o l a r d r i f t r e g i o n$ $W_{d r i f t} : d r i f t l a y er t hi c k n ess$
Cutoff frequency	$f_{T} = \frac{g _{m}}{2 π C _{in}}, C_{in} = C_{g s} + C_{g d}$	$f_{T} ≲ \frac{v _{s a t}}{2 π L} (see Metal-Semiconductor Field-Effect Transistor page)$	$C_{in} : in p u t c a p a c i t an ce (l a r g e in a S I T b ec a u se t h e g a t e r e g i o n s a r e in t er l e a v e d w i t h t h e c hann e l)$ $L : c hann e l l e n g t h$

Important Questions

Ques: Why is the SIT’s output characteristic triode-like, while a JFET’s saturates?

In a long-channel JFET the gate depletion region shields the source end of the channel from the drain voltage, so beyond pinch-off ( $V_{D s a t}$ ) extra drain voltage appears only across a small depleted segment and the current stays nearly constant (see the Junction Field-Effect Transistor page). In a SIT the channel is short and narrow, so the gate cannot fully screen the drain: the drain’s electric field penetrates to the saddle point and lowers the barrier directly, which is the $- α_{D} V_{D S}$ term in $ϕ_{B}$ . The current then keeps increasing with $V_{D S}$ exactly like a vacuum triode’s plate current, with $V_{e f f} = V_{GS} + V_{D S} / μ$ replacing the triode grid-plate combination, and the sharpness of this effect is measured by the amplification factor $μ = α_{G} / α_{D} = g_{m} r_{d}$ . Reference: J. Nishizawa, T. Terasaki, and J. Shibata, “Field-effect transistor versus analog transistor (static induction transistor),” IEEE Trans. Electron Devices ED-22, 185 (1975); S.M. Sze and Kwok K. Ng, Physics of Semiconductor Devices, 3rd ed., Wiley, 2007.

Ques: How does a SIT block high voltage, and what does the blocking gain mean?

Making the channel narrow and lightly doped so that $V_{P 0} < V_{bi}$ means the built-in depletion alone cuts off the channel, so the device blocks at zero gate bias (normally off). Applying a more negative gate voltage raises the barrier further, and since the drain lowers it only by $α_{D}$ per volt, the drain voltage that can be held off before the barrier collapses is about $μ (V_{T} - V_{GS})$ . The blocking gain, the ratio of blocked drain voltage to gate voltage magnitude, therefore tends toward $μ$ , which is why a larger $μ$ means a lower gate voltage is needed to block a given drain voltage. The practical ceiling is gate-drain avalanche breakdown. Reference: B.J. Baliga, Fundamentals of Power Semiconductor Devices, Springer, 2008.

Ques: What are the trade-offs that limited the SIT’s use in practice?

A normally-off SIT conducts only when the gate is brought near zero or slightly forward biased, and its channel is narrow, so its on-resistance is relatively high; operating it with a forward-biased gate (the bipolar-mode SIT) injects minority carriers that cause conductivity modulation, lowering $R_{o n}$ in the same way as in a PIN diode, but at the price of stored charge and slower switching. Even in unipolar mode, the closely spaced gate structure produces a large input capacitance $C_{in} = C_{g s} + C_{g d}$ , which limits $f_{T}$ below the transit-time estimate $v_{s a t} / (2 π L)$ . Together with the extra process complexity of a buried-gate vertical structure, this made the SIT a specialist power and high-frequency device, largely displaced in power electronics by MOSFETs and IGBTs. Reference: B.J. Baliga, Fundamentals of Power Semiconductor Devices, Springer, 2008.

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