Fin Field Effect Transistor (FinFET)

1. Theory

• Definition: A FinFET is a transistor whose channel is a tall, thin vertical silicon fin with the gate wrapped over it, conducting along both sidewalls.
• Vertical double gate: In the classic FinFET a thick hard mask disables the fin top, so the two sidewalls form a double-gate transistor turned on its side.
• Relation to tri-gate: If the top surface is also gated the device becomes a tri-gate transistor; for tall fins the difference is small.
• Effective width: Each fin contributes $2H_{fin}$ of gated width, and several fins are placed in parallel at a fin pitch $P_{fin}$.
• Width quantization: Transistor width can only change in whole-fin steps ($W_{total}=N_{fin}{W}_{eff,fin}$).
• Thin-fin requirement: Short-channel control needs $W_{fin}$ roughly $L/2$ to $L/3$, i.e. a few nanometres in advanced nodes.
• Undoped fin: The threshold is set by the gate work function; quantum confinement makes $V_{TH}$ very sensitive to fin width.

2. Working Principle

• Gate control from both sidewalls: The two gates hold the thin fin’s potential, shrinking the natural length ${\lambda }_{fin}$ and suppressing DIBL and roll-off.
• Near-ideal swing: A fully depleted fin approaches 60 mV/dec in long-channel devices.
• High drive per footprint: Tall fins pack more gated width into a given layout width than a planar transistor (advantage factor $W_{eff,fin}/P_{fin}$).
• Fin-width variability: Sub-nanometre variations in fin width cause noticeable threshold spread through confinement.
• Bulk vs SOI fins: SOI fins are fully isolated; bulk fins need a punch-through stopper and isolation oxide to block sub-fin leakage.

3. Applications

• Leading-edge logic (22 nm to 3 nm class): CPUs, GPUs, mobile application processors and AI accelerators.
• High-density SRAM caches: On-chip memory built from integer-fin pull-up, pull-down and access transistors.
• Advanced-node SoCs and FPGAs: Low-leakage, high-performance digital and mixed-signal chips.

Name	Formula	Related Formulae	Variables/Constants
Effective width per fin	$W_{eff,fin}=2H_{fin}$	$\begin{array}{r}{W}_{eff,fin}=2H_{fin}+W_{fin}\text{(top gate active)}\\ \text{(see Tri-Gate MOSFET page)}\end{array}$	$\begin{array}{r}{W}_{eff,fin}:\text{gated perimeter of one fin}\\ H_{fin}:\text{fin height}\\ W_{fin}:\text{fin width (thickness)}\end{array}$
Width quantization	$W_{total}=N_{fin}{W}_{eff,fin}$	$\begin{array}{r}{W}_{eff}/\text{footprint}=\frac{W_{eff,fin}}{P_{fin}}\\ \text{(drive per unit layout width)}\end{array}$	$\begin{array}{r}{N}_{fin}:\text{number of fins (an integer)}\\ P_{fin}:\text{fin pitch}\end{array}$ $\begin{array}{r}\text{(the transistor width can change only in}\\ \text{steps of one fin, not continuously)}\end{array}$
Natural length (fin as a double gate)	${\lambda }_{fin}=\sqrt{\frac{{\epsilon }_s}{2{\epsilon }_{ox}}\left(1+\frac{{\epsilon }_{ox}{W}_{fin}}{4{\epsilon }_s{t}_{ox}}\right)W_{fin}{t}_{ox}}$	$\begin{array}{r}{\lambda }_{fin}={\lambda }_{DG}\left(t_{Si}\to W_{fin}\right)\\ \text{(see Double-Gate MOSFET page)}\end{array}$	$\begin{array}{r}{\lambda }_{fin}:\text{natural length of the fin}\\ \text{(top gate neglected)}\end{array}$
Fin-width design rule	$W_{fin}\lesssim \frac{L}{2}\text{to}\frac{L}{3}$	$\begin{array}{r}L\gtrsim 5\text{to}6{\lambda }_{fin}\\ \text{(see Double-Gate MOSFET page)}\end{array}$	$\begin{array}{r}\text{(commonly quoted guideline for acceptable}\\ \text{short-channel behavior; the more rigorous}\\ \text{condition is the}{\lambda }_{fin}\text{rule)}\end{array}$
Threshold sensitivity to fin width	$\frac{d{V}_{TH}}{d{W}_{fin}}=-\frac{{\pi }^2{\hslash }^2}{q{m}^{\ast }{W}_{fin}^3}$	$\begin{array}{r}\Delta V_{TH}\approx \frac{E_1}{q},E_1=\frac{{\pi }^2{\hslash }^2}{2m^{\ast }{W}_{fin}^2}\\ \text{(see Double-Gate MOSFET page)}\end{array}$	$\begin{array}{r}\text{(derivative of the quantum-confinement}\\ \text{shift with respect to the fin width; it}\\ \text{grows rapidly as the fin is thinned)}\end{array}$
Drain current per fin	$I_{Dsat,fin}=\frac{{\mu }_n{C}_{ox}}{2m}\frac{W_{eff,fin}}{L}{\left(V_{GS}-V_{TH}\right)}^2$	$\begin{array}{r}{I}_D=N_{fin}{I}_{Dsat,fin}\\ m\approx 1\end{array}$	$\begin{array}{r}\text{(same as the double-gate expression with}\\ Z\to H_{fin}\text{; see Long Channel MOSFET}\\ \text{page)}\end{array}$
Drive current per layout width	$\frac{I_D}{W_{layout}}=\frac{I_{Dsat,fin}}{P_{fin}}$	$\begin{array}{r}\text{advantage over planar}=\frac{W_{eff,fin}}{P_{fin}}\end{array}$	$\begin{array}{r}{W}_{layout}:\text{layout width occupied by the fins}\\ \text{(a planar device of the same layout}\\ \text{width has an advantage factor of 1)}\end{array}$
Ideal long-channel subthreshold swing	$S\to \ln (10)\frac{k_{B}T}{q}\approx 60mV/dec$	$\begin{array}{r}L\gg {\lambda }_{fin}\\ \text{(see Double-Gate MOSFET page)}\end{array}$	$\begin{array}{r}\text{(requires a fully depleted fin; the}\\ \text{swing degrades in bulk fins with a leaky}\\ \text{sub-fin region)}\end{array}$ $k_B:Boltzmannconstant$

Important Questions

Ques: How does a FinFET differ from the tri-gate transistor?

Both use a gated fin, so the difference is only whether the top surface conducts. A classic FinFET carries a thick dielectric hard mask on the fin top, so only the two sidewalls are controlled by the gate and the effective width per fin is $2H_{fin}$; the structure is a double-gate transistor turned on its side, and the Double-Gate MOSFET page applies directly with $t_{Si}\to W_{fin}$. If the hard mask is removed or thinned so that the top is gated as well, the fin becomes a tri-gate transistor with $W_{eff}=W_{Si}+2H_{Si}$ and a slightly shorter natural length because of the third gate. In practice the distinction blurs for tall fins, since the top contributes little to the total width. Reference: D. Hisamoto et al., “FinFET - a self-aligned double-gate MOSFET scalable to 20 nm,” IEEE Trans. Electron Devices 47, 2320 (2000); B.S. Doyle et al., IEEE Electron Device Lett. 24, 263 (2003).

Ques: What does width quantization mean, and why does it matter for circuit design?

A FinFET’s width is set by how many fins are used, $W_{total}=N_{fin}{W}_{eff,fin}$, so the designer can change transistor strength only in whole fin steps, rather than by drawing any width as in a planar process. This complicates designs that rely on finely tuned width ratios, such as the pull-up, pull-down and access transistors of a static memory cell, which must be built from integer fin counts, and it makes mixed strengths in analog circuits more coarse. The compensating benefit is that each fin of height $H_{fin}$ packs a large gated perimeter into a small layout width, giving a drive-per-layout-width advantage of $W_{eff,fin}/P_{fin}$ over a planar device. Reference: J.-P. Colinge, FinFETs and Other Multi-Gate Transistors, Springer, 2008.

Ques: Why must the fin be so thin, and what does that do to variability?

Short-channel control depends on ${\lambda }_{fin}$, which grows with the fin width, so keeping $L\gtrsim 5$ to $6{\lambda }_{fin}$ (or the common guideline $W_{fin}\lesssim L/2$ to $L/3$) forces the fin to be thinner as the gate length shrinks, to only a few nanometers in advanced nodes. At such widths quantum confinement raises the threshold by $E_1/q$, and the derivative $d{V}_{TH}/d{W}_{fin}=-{\pi }^2{\hslash }^2/(q{m}^{\ast }{W}_{fin}^3)$ shows the threshold becomes steeply dependent on the exact fin width, so a fraction of a nanometer of fin-width or edge-roughness variation produces a noticeable threshold spread. Controlling fin width is consequently one of the dominant manufacturing and variability issues. Reference: Y. Taur and T.H. Ning, Fundamentals of Modern VLSI Devices, 2nd ed., Cambridge University Press, 2009; J.-P. Colinge, FinFETs and Other Multi-Gate Transistors, Springer, 2008.

Ques: What changes between FinFETs built on SOI wafers and on bulk silicon?

On SOI each fin sits on a buried oxide, so the fin is fully isolated and the coupling to the substrate is negligible, which gives the best subthreshold swing and low junction capacitance (see the Silicon-on-Insulator MOSFET page). On bulk silicon the fin is connected to the substrate below, so the bottom of the fin and the sub-fin region can form a leakage path between source and drain, and the capacitive coupling to the substrate worsens the swing. Bulk FinFET processes therefore add a heavily doped punch-through stopper and an isolation oxide around the fin base to suppress this leakage; the benefit is lower wafer cost and compatibility with existing bulk manufacturing. Reference: J.-P. Colinge, FinFETs and Other Multi-Gate Transistors, Springer, 2008.

Related pages in this vault: Tri-Gate MOSFET, Gate All Around Field Effect Transistor (GAAFET), Double-Gate MOSFET, Silicon on Insulator (SOI) MOSFET, Static Random Access Memory (SRAM), Long Channel MOSFET, Multi-Gate Models (BSIM-CMG and BSIM-IMG), Static and Dynamic Random Access Memory (SRAM and DRAM), CMOS Logic Transistors.