1. Theory

Definition: The power delivery network carries supply current from the voltage regulator through the board, package, bumps and on-chip grid to every transistor, and must keep the local supply within an allowed ripple, typically about 10 per cent, despite fast current changes (Popovich et al.; Olney).
Target impedance: The network’s impedance seen by the load must stay below $V_{D D} \cdot Ripple / I$ over the bandwidth of the load current, which falls by about a factor of two per technology generation as currents rise and supplies fall (Popovich et al.; Olney).
Drops: The supply sags by the resistive drop $I R$ along the grid, the inductive drop $L d I / d t$ in the package and grid, and the discharge of the decoupling capacitance during the current rise (Popovich et al.).
Decoupling: On-chip decaps supply fast current locally, but only within a limited distance of the load set by the grid resistance and inductance (Popovich et al.).
Backside power: Moving the power grid to the back of the wafer shortens the path to the transistors and frees front-side tracks, lowering IR droop by about 30 per cent in Intel’s PowerVia test chip (Tom’s Hardware).

2. Working Principle

Hierarchy of decoupling: Each level, from the regulator through board and package capacitors to on-die capacitance, supplies current over a frequency band, and the on-die capacitance covers the fastest edges because package inductance blocks them (Olney; background knowledge for the hierarchy).
First droop: When a block switches on, the on-die capacitance supplies the current until the package inductance responds; the package inductance and die capacitance resonate, typically at tens to hundreds of MHz, producing the largest droop (background knowledge).
Local droop: Within the die, the grid resistance and inductance between a decap and a switching block limit how much charge the decap can deliver in one rise time, so distant decaps are ineffective (Popovich et al.).
Static IR drop: The average current through the resistive grid lowers the supply over large areas, set by line resistance, via resistance and the density of supply bumps or vias (background knowledge).

3. Applications

PDN sign-off: Target-impedance and droop analysis of package and die, with impedance profiles by frequency band (Olney).
Decap planning: Sizing and placing MOS, MIM or trench decaps near high-current blocks (Popovich et al.; MOS and Poly-Insulator Capacitors and Deep-Trench Capacitors pages).
Grid design: Width and pitch of power lines on thick top metals, and bump and via density (Popovich et al.; background knowledge).
Backside power delivery: Intel PowerVia and similar schemes at the 2 $nm$ -class nodes (Tom’s Hardware; background knowledge for the node class).

Target Impedance and Droop

Name	Formula	Related Formulae	Variables/Constants
Target impedance	$Z_{t a r g e t} = \frac{V _{D D} \cdot Ripple}{I}$	$∣ Z_{P D N} (f) ∣ \leq Z_{t a r g e t} (up to the required bandwidth)$	$Z_{t a r g e t} : ma x im u m a l l o w e d im p e d an ce o f t h e p o w er d e l i v er y n e tw or k see n b y t h e l o a d$ $V_{D D} : s u ppl y v o l t a g e, R i ppl e : a l l o w e d f r a c t i o na l s u ppl y n o i se$ $I : t r an s i e n t c u r r e n t, Z_{P D N} (f) : im p e d an ce o f t h e n e tw or k a g ain s t f r e q u e n cy; P o p o v i c h e t a l . : E q . 1 in t hi s f or m, w i t h t h e t a r g e t im p e d an ce f a l l in g b y ab o u t a f a c t or o f tw o p er t ec hn o l o g y g e n er a t i o n; O l n ey : t h e t a r g e t se t b y t h e ma x im u m r ai l n o i se an d t h e w or s t - c a se t r an s i e n t c u r r e n t, w hi c h i s r a r e l y k n o w n a cc u r a t e l y, so an im p e d an ce p r o f i l e b y f r e q u e n cy ban d i s u se d in s t e a d, t r an s i e n t c u r r e n t co h er e n ce f a l l in g n e a r 1 GHz, an d o v er d es i g n w e l l b e l o w t a r g e t a dd in g cos t w i t h l i ttl e b e n e f i t$ $(co m p u t e d : 1 V w i t h 10 p er ce n t r i ppl e g i v es 0.1 Ω a t 1 A an d 1 mΩ a t an a ss u m e d 100 A)$
First droop and package resonance	$V_{l o a d} = V_{D D} - I R - L \frac{d I}{d t} - Δ V_{C}$	$f_{r es} \approx \frac{1}{2 π L _{p k g} C _{d i e}}, Z_{p e ak} \approx \frac{L _{p k g}}{C _{d i e}} (lightly damped)$	$V_{l o a d} : s u ppl y v o l t a g e a t t h e l o a d d u r in g t h e c u r r e n t r i se$ $I R : r es i s t i v e d r o p, L d I / d t : in d u c t i v e d r o p$ $Δ V_{C} : d r oo p o f t h e d eco u pl in g c a p a c i t or$ $f_{r es} : r eso nan ce o f t h e p a c k a g e in d u c t an ce L_{p k g} w i t h t h e o n - d i e c a p a c i t an ce C_{d i e}$ $Z_{p e ak} : a pp r o x ima t e im p e d an ce p e ak a t t ha t r eso nan ce (r eso nan ce f or m s, ba c k g r o u n d k n o w l e d g e); P o p o v i c h e t a l . : E q . 9 f or t h e l o a d v o l t a g e a t t h e f i r s t d r oo p; O l n ey : d eco u pl in g l oses e f f ec t ab o v e t h e c a p a c i t o r^{'} s ser i es r eso nan ce, an d a 460 pH t r a ce a g ain s t a 324 pH v ia p ai r an d pl an e s h o w s ab o u t 30 p er ce n t l ess in d u c t an ce$ $(co m p u t e d : an a ss u m e d 10 pH e f f ec t i v e p a c k a g e in d u c t an ce w i t h 500 nF o f d i e c a p a c i t an ce r eso na t es a t 71 MHz w i t h a c ha r a c t er i s t i c im p e d an ce o f 4.5 mΩ; 1 pH c a r r y in g 100 A in 1 ns d r o p s 0.1 V)$

Decoupling Capacitance

Name	Formula	Related Formulae	Variables/Constants
Minimum on-chip decoupling capacitance	$C_{d ec}^{f} \geq \frac{I _{ma x} ( t _{r} + t _{f} )}{0.2 V _{D D}}, C_{d ec}^{r} \geq \frac{I _{ma x} t _{r}}{2 ( 0.1 V _{D D} - I R - L d I / d t )}$	$Δ V_{C}^{r} = \frac{I _{ma x} t _{r}}{2 C _{d ec}}$	$C_{d ec}^{f} : d ec a p n ee d e d w h e n t h e seco n d d r oo p (a f t er t h e c u r r e n t p e ak) d o mina t es$ $C_{d ec}^{r} : d ec a p n ee d e d w h e n t h e f i r s t d r oo p d u r in g t h e r i se d o mina t es$ $I_{ma x} : p e ak l o a d c u r r e n t$ $t_{r}, t_{f} : r i se an d f a l l t im es o f t h e l o a d c u r r e n t, I R an d L d I / d t : d r o p s a l o n g t h e g r i d f r o m t h e d ec a p t o t h e l o a d$ $Δ V_{C}^{r} : d ec a p d r oo p d u r in g t h e r i se; P o p o v i c h e t a l . : w i t h V_{D D} = 1 V, 10 p er ce n t r i ppl e, t_{r} = 100 ps, t_{f} = 300 ps an d a 400 ps r ec ha r g e t im e, 100 mA l o a d s n ee d 357 pF o n t h e t o p l a y er an d 227 pF o n an in t er m e d ia t e l a y er, w hi l e 10 mA n ee d s 20 pF; M O S an d t r e n c h d ec a p d e n s i t i es o n t h e M O S an d P o l y - I n s u l a t or an d D ee p - T r e n c h C a p a c i t or s p a g es$ $(co m p u t e d : t h e seco n d - d r oo p b o u n d g i v es 200 pF f or 100 mA; 200 pF n ee d s 0.045 m m^{2} o f 4.4 fF/ μ m^{2} g a t e o x i d e b u t o n l y ab o u t 800 μ m^{2} o f a 250 fF/ μ m^{2} t r e n c h c a p a c i t or)$
Maximum effective distance of a decap	$d_{Z}^{ma x} = \frac{V _{D D} \cdot Ripple}{I r ^{2} + ω ^{2} l ^{2}}$	$d_{cr i t} = \frac{0.1 V _{D D} ( 1 - \frac{t _{r}}{t _{r} + t _{f}} )}{I r + l d I / d t}$	$d_{Z}^{ma x} : l a r g es t d i s t an ce f r o m t h e l o a d a t w hi c h a d ec a p s t i l l m ee t s t h e t a r g e t im p e d an ce$ $r, l : r es i s t an ce an d in d u c t an ce p er u ni t l e n g t h o f t h e g r i d l in e$ $ω : an g u l a r f r e q u e n cy se t b y t h e c u r r e n t r i se t im e$ $d_{cr i t} : cr i t i c a l d i s t an ce se p a r a t in g t h e seco n d - d r oo p (s h or t er) an d f i r s t - d r oo p (l o n g er) r e g im es; P o p o v i c h e t a l . : g r i d l in es o f 0.007 Ω/ μ m an d 0.5 pH/ μ m (t o p), 0.04 Ω/ μ m an d 0.3 pH/ μ m (in t er m e d ia t e) an d 0.1 Ω/ μ m an d 0.1 pH/ μ m (b o tt o m); t y p i c a l e f f ec t i v e r a d ii o f se v er a l h u n d r e d μ m; t h e r a d i u s f a l l s ab o u t l in e a r l y w i t h l o a d c u r r e n t an d, f or t h e c ha r g e - t im e cr i t er i o n, w i t h t h e s q u a r e o f t h e d ec a p; a t 1 A n o l a y er g i v es a r a d i u s o f e v e n o n e m es h ce l l, so l a r g e l o a d s m u s t b e p a r t i t i o n e d or d ec a p s pl a ce d c l oser; a d j a ce n t p o w er an d g r o u n d p a d s ab o u t 1300 μ m a p a r t in a 3000 - p in p a c k a g e$ $(n o co m p u t e d v a l u e : t h e p a p e r^{'} s m es h - ce l l s i z e i s n o t g i v e n in t h e s u mma r y)$

Grid and Backside Power

Name	Formula	Related Formulae	Variables/Constants
IR drop in a power grid	$Δ V_{I R} = \sum_{j} I_{j} R_{j} (along the path from pad or via to load)$	$R_{l in e} = r d, Δ V_{I R} \leq (share of Ripple) V_{D D}$	$Δ V_{I R} : s t a t i c or a v er a g e r es i s t i v e d r o p$ $I_{j}, R_{j} : c u r r e n t s an d r es i s t an ces o f g r i d se g m e n t s$ $R_{l in e} : r es i s t an ce o f a g r i d l in e o f l e n g t h d w i t h r es i s t an ce r p er l e n g t h (ba c k g r o u n d k n o w l e d g e f or t h e f or m s); P o p o v i c h e t a l . : t o p - l a y er p o w er l in es o f 0.007 Ω/ μ m an d p o w er an d g r o u n d p a d s ab o u t 1300 μ m a p a r t; e l ec t r o mi g r a t i o n l imi t s o n p o w er - g r i d c u r r e n t d e n s i t y o n t h e M e t a l an d I n t er co nn ec t p a g e$ $(co m p u t e d : a s in g l e t o p - l a y er l in e o v er ha l f t h e p a d s p a c in g, 650 μ m, ha s 4.6 Ω, so t h e g r i d n ee d s man y l in es in p a r a l l e l)$
Backside power delivery	$\frac{Δ V _{I R, B S P D}}{Δ V _{I R, F S}} \approx 0.7 (Intel PowerVia test chip)$	$N_{l a y er s} = N_{f r o n t} + N_{ba c k}$	$Δ V_{I R, B S P D}, Δ V_{I R, F S} : I R d r oo p w i t h ba c k s i d e an d w i t h f r o n t - s i d e p o w er d e l i v er y$ $N_{l a y er s} : t o t a l m e t a l l a y er s; T o m^{'} s H a r d w a r e (I n t e l^{'} s V L S I 2023 r es u l t s) : t h e I n t e l 4 pl u s P o w er V ia t es t c hi p w i t h C r es t m o n t E - cor es t a r g e t in g 3 GHz a t 1.1 V r e d u ce d I R d r oo p b y 30 p er ce n t, r ai se d c l oc k s p ee d b y o v er 6 p er ce n t an d r e a c h e d ce l l u t i l i z a t i o n ab o v e 90 p er ce n t o v er l a r g e a r e a s, w i t h 14 f r o n t - s i d e an d 4 ba c k s i d e l a y er s pl u s R D L a g ain s t 15 l a y er s pl u s R D L f or I n t e l 4, n e a r l y t h e s am e d e f ec t d e n s i t y an d t h er ma l s in l in e w i t h e x p ec t a t i o n s; p o w er r e a c h es t h e t r an s i s t or s f r o m b e l o w t h r o ug h nan o - T S V s, f r ee in g f r o n t - s i d e t r a c k s f or s i g na l s (ba c k g r o u n d k n o w l e d g e f or t h e m ec hani s m)$ $(co m p u t e d : 18 a g ain s t 15 m e t a l l a y er s, 3 m or e in t o t a l)$

Important Questions

Ques: How small must the impedance of a modern power delivery network be?

The target impedance is $V_{D D} \cdot Ripple / I$ , as in Popovich et al.’s Eq. 1. With a 1 $V$ supply and 10 per cent ripple it is 0.1 $Ω$ for a 1 A load but 1 $mΩ$ for an assumed 100 A processor (computed), and Popovich et al. note that it falls by about a factor of two each generation. Olney adds that the transient current is rarely known accurately, that its coherence falls near 1 $GHz$ , and that the target therefore becomes an impedance profile that can differ by frequency band and location, rather than a single number. Designing far below the target adds cost with little benefit. The difficulty is that package and bump inductance make milliohm impedances hard to hold at high frequency, which is why on-die capacitance and closely spaced bumps are needed. Reference: M. Popovich, E. G. Friedman, M. Sotman, A. Kolodny and R. M. Secareanu, ‘Maximum Effective Distance of On-Chip Decoupling Capacitors in Power Distribution Grids’, GLSVLSI 2006 (Technion copy) (fetch-tool summary); B. Olney (In-Circuit Design), ‘Beyond Design: The Target Impedance Approach to PDN Design’, application note AN2018_1 (2018) (fetch-tool summary).

Ques: Why is the first droop usually the worst supply dip?

Because the package inductance and the on-die capacitance form a resonant circuit. When a large block switches on, the die capacitance supplies the current first, and the package current builds up only at a rate set by its inductance, so the supply dips and rings at about $1/ (2 π L_{p k g} C_{d i e})$ (background knowledge). For an assumed 10 $pH$ effective package inductance and 500 $nF$ of die capacitance, this is about 71 $MHz$ , with a characteristic impedance of about 4.5 $mΩ$ (computed), already above a 1 $mΩ$ target. Even 1 $pH$ carrying 100 A in 1 $ns$ gives 0.1 $V$ of inductive drop (computed). Popovich et al. write the load voltage as $V_{D D} - I R - L d I / d t - Δ V_{C}$ , which shows how the inductive drop and the decap droop add during the rise. Reference: M. Popovich, E. G. Friedman, M. Sotman, A. Kolodny and R. M. Secareanu, ‘Maximum Effective Distance of On-Chip Decoupling Capacitors in Power Distribution Grids’, GLSVLSI 2006 (Technion copy) (fetch-tool summary).

Ques: How much on-chip decoupling capacitance does a switching block need?

Popovich et al. give two bounds. When the droop after the current peak dominates, $C_{d ec} \geq I_{ma x} (t_{r} + t_{f}) / (0.2 V_{D D})$ , which for 100 $mA$ with 100 $ps$ rise and 300 $ps$ fall at 1 $V$ gives 200 $pF$ (computed). When the droop during the rise dominates, the grid’s $I R$ and $L d I / d t$ between decap and load eat into the 10 per cent budget, and their case study needed 357 $pF$ on the top layer and 227 $pF$ on an intermediate layer for 100 $mA$ , against 20 $pF$ for 10 $mA$ . With 4.4 $fF/ μ m^{2}$ of gate oxide, 200 $pF$ takes about 0.045 $m m^{2}$ , but a 250 $fF/ μ m^{2}$ trench capacitor needs only about 800 $μ m^{2}$ (computed), which is one reason trench decaps are used in high-performance processors. Reference: M. Popovich, E. G. Friedman, M. Sotman, A. Kolodny and R. M. Secareanu, ‘Maximum Effective Distance of On-Chip Decoupling Capacitors in Power Distribution Grids’, GLSVLSI 2006 (Technion copy) (fetch-tool summary); MOS and Poly-Insulator Capacitors page of this vault; Deep-Trench Capacitors page of this vault.

Ques: How far from a load can a decoupling capacitor be and still help?

Popovich et al. define a maximum effective distance from the target impedance, $V_{D D} \cdot Ripple / (I r^{2} + ω^{2} l^{2})$ , and a second limit from the time needed to recharge the decap through the grid. With grid lines of 0.007 $Ω/ μ m$ and 0.5 $pH/ μ m$ on the top layer, 0.04 $Ω/ μ m$ and 0.3 $pH/ μ m$ on an intermediate layer and 0.1 $Ω/ μ m$ and 0.1 $pH/ μ m$ on the bottom layer, a 10 $mA$ load could use decaps more than 40 mesh cells away, a 100 $mA$ load only less than one to two cells, and a 1 A load less than one cell on any layer. The radius falls about linearly with load current and, for the recharge criterion, with the square of the capacitance. Large loads must therefore be split into smaller blocks with decaps placed among them. Reference: M. Popovich, E. G. Friedman, M. Sotman, A. Kolodny and R. M. Secareanu, ‘Maximum Effective Distance of On-Chip Decoupling Capacitors in Power Distribution Grids’, GLSVLSI 2006 (Technion copy) (fetch-tool summary).

Ques: How much does backside power delivery improve IR drop and performance?

Intel’s PowerVia test chip, reported by Tom’s Hardware from its 2023 VLSI results, put Crestmont E-cores on Intel 4 with the power network moved to the back of the wafer. It reduced IR droop by 30 per cent, raised clock speed by over 6 per cent and allowed cell utilization above 90 per cent over large areas, because signals no longer share front-side tracks with wide power lines (background knowledge for the mechanism). The stack grew from 15 metal layers plus RDL to 14 front-side and 4 backside layers plus RDL, three more in total (computed), while defect density stayed nearly the same and thermals were in line with expectations. The gain comes from a much shorter, lower-resistance path from bumps to transistors, through nano-TSVs instead of the full front-side stack. Reference: Tom’s Hardware, ‘Intel Details PowerVia Backside Power Delivery Technology’ (6 June 2023), reporting Intel’s VLSI 2023 test-chip results (fetch-tool summary).

Ques: Why must a power grid be built from many parallel lines?

Because a single line is far too resistive for the currents involved. Popovich et al. give 0.007 $Ω/ μ m$ for a top-layer power line and about 1300 $μ m$ between adjacent power and ground pads. Over half that spacing, 650 $μ m$ , one such line has about 4.6 $Ω$ , so 100 $mA$ would drop 0.46 $V$ (computed), almost half of a 1 $V$ supply. A mesh of many lines in parallel on several layers, fed from bumps or vias at close spacing, divides this resistance by the number of parallel paths. The same grid must also keep current density below electromigration limits, which sets a minimum metal width per unit current. Thick top metals carry most of the current, and backside power removes the need to pass it down through the signal layers. Reference: M. Popovich, E. G. Friedman, M. Sotman, A. Kolodny and R. M. Secareanu, ‘Maximum Effective Distance of On-Chip Decoupling Capacitors in Power Distribution Grids’, GLSVLSI 2006 (Technion copy) (fetch-tool summary); Metal and Interconnect page of this vault (Reliability and Degradation, Stress Types).

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Power Delivery Networks