1. Theory
- Definition: A nanocrystal (nanodot) memory is a MOSFET whose floating gate is replaced by a layer of isolated semiconductor (Si, Ge) or metal (Pt, Au, W) nanocrystals embedded in the gate oxide.
- Discrete storage: Each dot holds a few electrons and is isolated by oxide, so a tunnel-oxide defect discharges only one dot (lost fraction ).
- Thin tunnel oxide: Defect tolerance allows a 3–5 nm tunnel oxide with direct tunnelling, giving lower voltage and faster programming.
- Charging energy: The dot self-capacitance makes each added electron cost energy (Coulomb blockade), limiting electrons per dot.
- Quantum confinement: In semiconductor dots, confinement raises the lowest level in proportion to , lowering the effective barrier.
- Material choice: Metal dots offer a larger barrier and no confinement penalty but risk contamination; Si dots are process-compatible.
2. Working Principle
- Program: Electrons tunnel directly (or by Fowler-Nordheim or hot-carrier injection) from the channel into the dots, raising .
- Erase: Reverse gate bias pulls the electrons back to the channel.
- Threshold window: , typically around 0.5 V for dots per with one electron each.
- Retention vs speed: Each extra 0.2 nm or so of tunnel oxide gains about a decade of retention but slows programming by the same factor.
- Dot spacing: Dots must be several nanometres apart to prevent lateral tunnelling and coalescence, capping the density.
- Variability: Spread in dot size and position causes threshold variation, especially in small devices where single electrons matter.
3. Applications
- Current status: Limited commercial use; overtaken by nitride charge-trap and split-gate cells.
- Embedded flash in microcontrollers: Silicon-nanocrystal storage has been used in some automotive and industrial MCU embedded flash.
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Areal density, coverage and spacing of the nanocrystals | |||
| Self-capacitance and charging energy (constant interaction model) | |||
| Quantum confinement energy | |||
| Barrier height for a stored electron | |||
| Threshold voltage shift | |||
| Threshold shift per electron in a small device | |||
| Direct tunnelling and its effect on retention | |||
| Loss of charge through a single oxide defect | |||
| Lateral tunnelling between neighboring nanocrystals |
Important Questions
Ques: What is a nanocrystal memory, and how does it differ from a floating-gate cell?
A nanocrystal memory is a MOSFET in which the floating gate is replaced by a layer of isolated nanometer-sized semiconductor or metal dots, embedded in the gate oxide between a thin tunnel oxide and a control oxide. Each dot stores a few electrons, and the dots are separated by oxide, so the charge is not shared. A defect in the tunnel oxide then discharges only the dot above it () instead of the whole gate. This allows a thin tunnel oxide of 3 to 5 nm, with direct tunnelling for programming, so the voltage can be lower and the speed higher, at the cost of a smaller window. Reference: S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E.F. Crabbe and K. Chan, “A silicon nanocrystals based memory,” Appl. Phys. Lett. 68, 1377 (1996).
Ques: Why is the memory window of a nanocrystal cell small, and how large is it?
The window is , so it is set by the number of stored electrons per area. For , one electron per dot and nm, this gives about 0.5 V. The density cannot be raised much, because the dots must be spaced by several nanometers to avoid lateral transfer and coalescence, and the Coulomb charging energy limits the number of electrons per dot to a few. The window is therefore smaller than that of a floating gate with a continuous plate. Reference: S. Tiwari et al., “Volatile and non-volatile memories in silicon with nano-crystal storage,” IEDM Tech. Dig., 1995, p. 521.
Ques: Why does the charging energy matter?
The self-capacitance of a dot of diameter is , so the energy needed to add one electron is of the order of and increases as the dot shrinks. When it exceeds the charging occurs in steps (Coulomb blockade), which tends to make the number of electrons per dot uniform, and each added electron lowers the barrier seen by the next (). In a semiconductor dot the quantum confinement energy also raises the lowest electron level, so both effects reduce the barrier for the stored electron. Reference: S. Tiwari et al., Appl. Phys. Lett. 68, 1377 (1996).
Ques: How do silicon, germanium and metal nanocrystals compare?
Silicon dots are compatible with the existing process, but their barrier ( V) is reduced by the confinement and charging energies. Germanium has nearly the same electron affinity as silicon (about 4.0 eV), so its electron barrier is similar, but its smaller bandgap puts the valence band higher, which changes hole storage, and Ge dots can be formed at a lower temperature. Metal dots such as Pt, Au or W have a large work function (about 5.6, 5.1 and 4.6 eV), so the barrier and the retention can be greater, their density of states is high so the charge is held at a well-defined level, and they have no quantum confinement penalty. However, many metals diffuse and form deep traps in silicon, which raises contamination and process-compatibility problems. Reference: Z. Liu, C. Lee, V. Narayanan, G. Pei and E.C. Kan, “Metal nanocrystal memories - Part I: Device design and fabrication,” IEEE Trans. Electron Devices 49, 1606 (2002).
Ques: How does the tunnel oxide thickness set the trade-off between retention and programming speed?
The transmission through the tunnel oxide falls as with , so each 0.2 nm of added oxide extends the retention by about a decade and lowers the program current by the same factor. A tunnel oxide of 3 nm programs quickly at low voltage but loses charge fast. A tunnel oxide of 4 to 5 nm has good retention but needs a higher voltage and field. The estimate is a rectangular-barrier calculation and the true behavior also depends on the field and on the traps in the oxide. Reference: S. Tiwari et al., IEDM Tech. Dig., 1995, p. 521; J. Brewer and M. Gill (eds.), Nonvolatile Memory Technologies with Emphasis on Flash, Wiley-IEEE Press, 2008.
Ques: How does a nanocrystal cell compare with a charge trap cell?
Both store charge in discrete sites, which gives a localized charge loss and thin tunnel layers. In a nitride charge trap cell the sites are structural defects, whose density, energy and capture cross section are fixed by the material and vary with the process. In a nanocrystal cell the storage sites are engineered by the choice of the material, the size and the density of the dots, so the barrier height and the number of electrons per site can be tuned. The nanocrystal cell is, however, harder to fabricate uniformly, because the dispersion of dot size and position causes spreads in the threshold voltage. Reference: J. Brewer and M. Gill (eds.), Nonvolatile Memory Technologies with Emphasis on Flash, Wiley-IEEE Press, 2008.
Related pages in this vault: Charge Trap Flash Memory (SONOS, TANOS and 3D NAND), EPROM, EEPROM and Legacy Non-Volatile Cells (FAMOS, FLOTOX, Split-Gate), Floating Gate Flash Memory (NOR and NAND), Organic Charge Trap Transistor Memory (Polymer Electret and Nanoparticle), Floating Gate and Charge-Trap Flash Memory (NOR, NAND and 3D NAND), Ferroelectric Tunnel Junction (FTJ), Floating Body Random Access Memory (Capacitorless 1T DRAM).