EPROM, EEPROM and Legacy Non-Volatile Cells (FAMOS, FLOTOX, Split-Gate)

1. Theory

Scope: The early floating-gate memory cells: the FAMOS avalanche-injection cell, the UV-erasable EPROM, the FLOTOX EEPROM, the over-erase problem of early flash, and the split-gate cell.
Common principle: Each stores charge on a polysilicon floating gate inside the gate oxide, shifting the threshold voltage, as on the Floating Gate Flash page.
FAMOS: The first floating-gate cell, a p-channel device programmed by avalanche injection of electrons from the broken-down p+ drain junction.
EPROM: A stacked-gate, one-transistor cell programmed by hot electrons and erased only by ultraviolet light through a quartz window.
FLOTOX EEPROM: A thin (8–10 nm) tunnel-oxide window over the drain allows electrical write and erase by Fowler-Nordheim tunnelling; a select transistor gives byte-level selection.
Split-gate cell: A select-gate channel section in series with the floating-gate section blocks over-erased cells from leaking and enables source-side injection programming.
MNOS heritage: The nitride-trapping MNOS cell is the ancestor of SONOS and charge-trap flash.

2. Working Principle

EPROM program: Drain at about 6 to 8 V and gate at about 12 V inject channel hot electrons onto the floating gate.
EPROM UV erase: Photons above the 3.1 eV barrier eject electrons by internal photoemission; the whole chip is erased in tens of minutes.
EEPROM write and erase: Electrons tunnel in (high gate, drain at 0 V) or out (gate at 0 V, high drain) through the window, byte by byte.
Over-erase: Removing too many electrons leaves a negative threshold; the cell then leaks with its gate at 0 V and corrupts reads on the bit line.
Over-erase fixes: ETOX uses erase-verify and reprogramming; the split-gate cell’s select section cuts the leakage path.
Endurance and retention: Repeated tunnelling builds traps in the window oxide that close the window and raise stress-induced leakage.

3. Applications

Serial EEPROM (FLOTOX): Byte-alterable storage of configuration, calibration and identification data, and smart-card memory.
Embedded flash in microcontrollers (split-gate): Code and data storage in MCUs and automotive and industrial controllers.
Current status of EPROM and FAMOS: Obsolete; replaced by flash and one-time-programmable memories.

Name	Formula	Related Formulae	Variables/Constants
Drain avalanche breakdown (FAMOS programming)	$B V = \frac{ε _{s} E _{c}^{2}}{2 q N _{B}}$	$M = \frac{1}{1 - ( V _{D} / B V ) ^{n}}$ $I_{G} = P_{inj} (M - 1) I_{D 0}$	$B V : a v a l an c h e b r e ak d o w n v o l t a g e o f t h e o n e - s i d e d ab r u pt d r ain j u n c t i o n$ $ε_{s} : se mi co n d u c t or p er mi tt i v i t y$ $E_{c} : cr i t i c a l f i e l d f or a v a l an c h e b r e ak d o w n$ $N_{B} : d o p in g o f t h e l i g h tl y d o p e d s i d e (t h e n - t y p e s u b s t r a t e o f t h e p - c hann e l F A M O S)$ $M : a v a l an c h e m u l t i pl i c a t i o n f a c t or (M i l l er e m p i r i c a l f or m), w i t h n t h e M i l l er e x p o n e n t$ $V_{D} : d r ain v o l t a g e d u r in g p r o g r ammin g$ $I_{D 0} : l e ak a g e c u r r e n t e n t er in g t h e a v a l an c h e r e g i o n$ $P_{inj} : p r o babi l i t y t ha t a h o t c a r r i er g e n er a t e d in t h e a v a l an c h e r e g i o n i s inj ec t e d o v er t h e o x i d e ba r r i er in t o t h e f l o a t in g g a t e$ $I_{G} : inj ec t i o n c u r r e n t in t o t h e f l o a t in g g a t e, w hi c h r e q u i r es a d r ain v o l t a g e n e a r B V (a f e w t e n s o f v o l t s in ma g ni t u d e f or t h e e a r l y p - c hann e l ce l l s)$ $(I_{G} i s a sc h e ma t i c c hain, l e ak a g e t im es m u l t i pl i c a t i o n t im es inj ec t i o n p r o babi l i t y, f or or d er s o f ma g ni t u d e o n l y)$
Programming time (hot-electron injection)	$t_{p r o g} \approx \frac{∣ Q _{F G} ∣}{I ˉ _{G}} = \frac{C _{I P D} ∣ Δ V _{T} ∣}{I ˉ _{G}}$	$I_{G} = I_{D} P_{inj}$ $P_{inj} \propto exp (- \frac{ϕ _{B}}{λ E _{m}})$	$t_{p r o g} : t im e t o s hi f t t h e t h r es h o l d v o l t a g e b y Δ V_{T}$ $Q_{F G} : c ha r g e pl a ce d o n t h e f l o a t in g g a t e$ $\overset{ˉ}{I}_{G} : a v er a g e inj ec t i o n c u r r e n t d u r in g t h e p u l se$ $C_{I P D} : c a p a c i t an ce b e tw ee n t h e co n t r o l g a t e an d t h e f l o a t in g g a t e$ $Δ V_{T} : t h r es h o l d v o l t a g e s hi f t see n f r o m t h e co n t r o l g a t e$ $(I_{G} d ecr e a ses a s t h e f l o a t in g g a t e c ha r g es b ec a u se V_{F G} an d t h e inj ec t i o n f i e l d f a l l, so t h e p r o g r ammin g s a t u r a t es; see t h e F l o a t in g G a t e F l a s h p a g e f or t h e l u c k y - e l ec t r o n m o d e l)$
Photoemission yield (UV erase)	$Y (h ν) = C_{Y} (h ν - q ϕ_{B})^{2} (h ν > q ϕ_{B})$	$h ν = \frac{1.24 eV μ m}{λ}$ $t_{er a se} \approx \frac{C _{I P D} ∣ Δ V _{T} ∣}{q Y Φ _{p h} A _{p h}}$	$Y : p h o t oe mi ss i o n y i e l d, t h e n u mb er o f e l ec t r o n s l e a v in g t h e f l o a t in g g a t e p er ab sor b e d p h o t o n (F o w l er l a w n e a r t h e t h r es h o l d)$ $C_{Y} : co n s t an t t ha t d e p e n d s o n t h e ma t er ia l an d t h e t e m p er a t u r e$ $h ν : p h o t o n e n er g y, w i t h λ t h e w a v e l e n g t h$ $q ϕ_{B} : ba r r i er h e i g h t b e tw ee n t h e f l o a t in g g a t e an d t h e o x i d e (ab o u t 3.1 e V), so l i g h t o f w a v e l e n g t h b e l o w ab o u t 400 nm c an er a se$ $t_{er a se} : e x p os u r e t im e f or a s hi f t Δ V_{T} (λ = 253.7 nm cor r es p o n d s t o 4.9 e V)$ $Φ_{p h} : p h o t o n f l ux d e n s i t y a t t h e f l o a t in g g a t e$ $A_{p h} : f l o a t in g g a t e a r e a r e a c h e d b y t h e l i g h t$ $(t h e s q u a r e d F o w l er l a w i s t h e m e t a l, n e a r - t h r es h o l d f or m; f or d e g e n er a t e p o l y s i l i co n an d w i t h an o x i d e f i e l d t h e e x p o n e n t an d C_{Y} c han g e . t_{er a se} a ss u m es e v er y e mi tt e d e l ec t r o n i s co l l ec t e d an d i g n or es t h e l i g h t l os t in t h e co n t r o l g a t e an d t h e f a l l in g y i e l d a s t h e g a t e d i sc ha r g es; E P R O M d a t a s h ee t s q u o t e an er a se d ose o f ab o u t 15 W s / c m^{2} a t 253.7 nm)$
Thermionic charge loss over the oxide barrier	$J_{t h} = A^{*} T^{2} exp (- \frac{q ϕ _{B}}{k _{B} T})$	$exp (- \frac{q ϕ _{B}}{k _{B} T}) \approx 1 0^{- 52} (ϕ_{B} = 3.1 V, T = 300 K)$	$J_{t h} : c u r r e n t d e n s i t y o f e l ec t r o n s e mi tt e d t h er ma l l y f r o m t h e f l o a t in g g a t e o v er t h e ba r r i er$ $A^{*} : e f f ec t i v e R i c ha r d so n co n s t an t$ $ϕ_{B} : ba r r i er h e i g h t in v o l t s$ $T : ab so l u t e t e m p er a t u r e$ $(t h e n u mb er s h o w s t ha t t h e ba r r i er i t se l f h o l d s t h e c ha r g e; a c t u a l r e t e n t i o n l oss co m es f r o m o x i d e d e f ec t s an d co n t amina t i o n)$ $k_{B} : B o l t z mann co n s t an t$
FLOTOX tunnel window	$I_{t u n} = A_{w in} J_{F N} (E_{t u n})$	$E_{t u n} = \frac{V _{F G} - V _{D}}{t _{w in}}$ $V_{F G} = α_{G} V_{C G} + α_{D} V_{D} + \frac{Q _{F G}}{C _{T}}$	$I_{t u n} : t u nn e l c u r r e n t t h r o ug h t h e t hin o x i d e w in d o w o v er t h e d r ain$ $A_{w in} : a r e a o f t h e t u nn e l w in d o w$ $J_{F N} : F o w l er - N or d h e im c u r r e n t d e n s i t y (see t h e F l o a t in g G a t e F l a s h p a g e)$ $E_{t u n} : f i e l d in t h e w in d o w o x i d e, p os i t i v e w h e n e l ec t r o n s f l o w f r o m t h e d r ain t o t h e f l o a t in g g a t e$ $t_{w in} : w in d o w o x i d e t hi c k n ess (ab o u t 8 t o 10 nm; d r ain s u r f a ce d e pl e t i o n an d f l a t - ban d o f f se t s a r e n e g l ec t e d in E_{t u n})$ $V_{F G}, V_{D}, V_{C G} : f l o a t in g g a t e, d r ain an d co n t r o l g a t e v o l t a g es$ $α_{G}, α_{D} : co u pl in g r a t i os o f t h e f l o a t in g g a t e t o t h e co n t r o l g a t e an d t o t h e d r ain$ $(a w r i t e u ses a hi g h V_{C G} w i t h V_{D} = 0 an d an er a se u ses V_{C G} = 0 w i t h a hi g h V_{D})$
Endurance of a tunnelling cell	$N_{cy c} \approx \frac{Q _{B D}}{2 Q _{p u l se}}$	$Q_{p u l se} = \int J_{F N} (E_{t u n} (t)) d t$	$N_{cy c} : es t ima t e d n u mb er o f w r i t e - er a se cy c l es b e f or e t h e w in d o w o x i d e f ai l s$ $Q_{B D} : c ha r g e - t o - b r e ak d o w n p er u ni t a r e a o f t h e w in d o w o x i d e$ $Q_{p u l se} : c ha r g e f l u e n ce p er u ni t a r e a o f o n e w r i t e or er a se p u l se$ $J_{F N} : t u nn e l c u r r e n t d e n s i t y d u r in g t h e p u l se$ $(t r a pp e d c ha r g e in t h e o x i d e c l oses t h e w in d o w b e f or e b r e ak d o w n, so t hi s i s an u pp er b o u n d)$
Over-erase leakage (stacked-gate cell)	$I_{o f f} (V_{T}) = I_{0} \frac{W}{L} exp (- \frac{V _{T}}{n ϕ _{t}}) (V_{C G} = 0)$	$I_{co l} = \sum_{i} I_{o f f} (V_{T, i})$	$I_{o f f} : l e ak a g e o f a ce l l w i t h i t s co n t r o l g a t e a t 0 V w h e n i t s t h r es h o l d v o l t a g e V_{T} i s l o w er e d b y an er a se t ha t r e m o v e d t oo man y e l ec t r o n s$ $I_{0} : t ec hn o l o g y - d e p e n d e n t c u r r e n t p r e f a c t or$ $n : s u b t h r es h o l d s l o p e f a c t or$ $ϕ_{t} : t h er ma l v o l t a g e k_{B} T / q$ $I_{co l} : t o t a l l e ak a g e o f t h e u n se l ec t e d ce l l s s ha r in g a bi t l in e, w hi c h c an ma s k t h e r e a d c u r r e n t o f t h e se l ec t e d ce l l$ $V_{T, i} : t h r es h o l d v o l t a g e o f t h e i - t h u n se l ec t e d ce l l (n e g a t i v e f or an o v er - er a se d ce l l; a l l ce l l s a t t h e s am e d r ain v o l t a g e, D I B L n e g l ec t e d)$ $k_{B} : B o l t z mann co n s t an t$
Split-gate cell resistance	$R_{ce l l} = R_{S G} + R_{F G}$	$R_{S G} = \frac{L _{S G}}{μ _{n} C _{o x} W ( V _{S G} - V _{T, S G} )}$ $R_{F G} = \frac{L _{F G}}{μ _{n} C _{t u n} W α _{G} ( V _{C G} - V _{T} )}$	$R_{ce l l} : c hann e l r es i s t an ce o f t h e tw o c hann e l sec t i o n s in ser i es (l in e a r r e g i o n)$ $R_{S G}, R_{F G} : r es i s t an ces o f t h e se l ec t - g a t e an d t h e f l o a t in g - g a t e sec t i o n s$ $L_{S G}, L_{F G} : l e n g t h s o f t h e tw o sec t i o n s$ $V_{S G}, V_{T, S G} : se l ec t g a t e v o l t a g e an d i t s t h r es h o l d$ $C_{t u n} : t u nn e l o x i d e c a p a c i t an ce p er u ni t a r e a$ $α_{G} : g a t e co u pl in g r a t i o o f t h e f l o a t in g g a t e sec t i o n$ $(t h e se l ec t g a t e c u t s t h e c hann e l e v e n i f t h e f l o a t in g g a t e sec t i o n ha s a n e g a t i v e t h r es h o l d, w hi c h r e m o v es t h e o v er - er a se p r o b l e m)$
Retention bake acceleration	$A F = exp [\frac{E _{a}}{k _{B}} (\frac{1}{T _{u se}} - \frac{1}{T _{s t r ess}})]$	$t_{u se} = A F t_{s t r ess}$	$A F : a cce l er a t i o n f a c t or o f t h e hi g h - t e m p er a t u r e bak e$ $E_{a} : a c t i v a t i o n e n er g y o f t h e c ha r g e - l oss m ec hani s m (i t m u s t b e m e a s u r e d f or t h e t ec hn o l o g y)$ $T_{u se}, T_{s t r ess} : o p er a t in g an d bak e t e m p er a t u r es in k e l v in$ $t_{u se} : e q u i v a l e n t d a t a r e t e n t i o n t im e a t t h e o p er a t in g t e m p er a t u r e$ $t_{s t r ess} : r e t e n t i o n t im e m e a s u r e d a t t h e bak e t e m p er a t u r e$ $(v a l i d o n l y i f t h e s am e m ec hani s m d o mina t es a t b o t h t e m p er a t u r es)$ $k_{B} : B o l t z mann co n s t an t$

Important Questions

Ques: How does an EPROM cell differ from an ordinary MOSFET, and how is it programmed and erased?

An EPROM cell is a MOSFET with a polysilicon floating gate between the channel and the control gate, so it has the same structure as the floating-gate flash cell. Programming uses channel hot-electron injection (drain near 6 to 8 V and gate near 12 V) or, in the earlier FAMOS cell, avalanche injection, and the electrons trapped on the floating gate raise the threshold voltage. The cell has no electrical erase. Ultraviolet light of photon energy above the 3.1 eV barrier gives electrons enough energy to leave the floating gate by internal photoemission, which is why the package has a quartz window. The cell is small (one transistor), but it is erased only as a whole chip. Reference: D. Frohman-Bentchkowsky, “Memory behavior in a floating-gate avalanche-injection MOS (FAMOS) structure,” Appl. Phys. Lett. 18, 332 (1971); R.H. Fowler, Phys. Rev. 38, 45 (1931).

Ques: Why does a FLOTOX EEPROM need a select transistor, and what is the tunnel window?

In a FLOTOX cell the floating gate overlaps the n+ drain through a thin oxide window of about 8 to 10 nm, and Fowler-Nordheim tunnelling through this window both writes and erases the cell (electrons in with a high gate voltage and the drain at 0 V, electrons out with the gate at 0 V and a high drain voltage). The names differ between manufacturers: in many FLOTOX papers the electron-injecting operation, which sets the high threshold, is called erase and the removal of electrons is called write or program. Since either operation can happen to any cell on the selected bit line, a series select transistor is added so that a single byte can be selected. This makes the cell two transistors large, but it allows byte-by-byte electrical erasing, which is the point of the EEPROM. Reference: G. Cappelletti, C. Golla, P. Olivo and E. Zanoni, Flash Memories, Kluwer, 1999; W. Johnson, G. Perlegos, A. Renninger, G. Kuhn and T. Ranganath, “A 16Kb electrically erasable nonvolatile memory,” ISSCC Dig. Tech. Papers, 152 (1980).

Ques: What is over-erase, and how do ETOX and split-gate cells deal with it?

In a stacked-gate cell without a select transistor, erasing can remove more electrons than needed and leave a negative threshold voltage. The cell then conducts with its control gate at 0 V ( $I_{o f f} \propto e^{- V_{T} / n ϕ_{t}}$ ), and the leakage summed over a bit line ( $I_{co l}$ ) can make an unselected cell look like a programmed one. ETOX (EPROM tunnel oxide) is Intel’s stacked-gate one-transistor flash cell: an EPROM-like cell programmed by channel hot electrons, with a thin tunnel oxide that allows Fowler-Nordheim erase from the source. It controls the erase with a verify loop, by programming the cell back until the threshold is within the window. The split-gate cell places a select-gate channel section in series with the floating-gate section, so a cell with a negative floating-gate threshold is still cut off, and it also lowers the programming current by using source-side injection. Reference: J. Brewer and M. Gill (eds.), Nonvolatile Memory Technologies with Emphasis on Flash, Wiley-IEEE Press, 2008.

Ques: Why can the UV erase of an EPROM not be done selectively or electrically?

The photoemission yield $Y \propto (h ν - q ϕ_{B})^{2}$ applies to any electron in the polysilicon floating gate, so the whole chip is discharged at once, and the light cannot be aimed at one cell. The process is also slow (typically tens of minutes under 253.7 nm light), because only a small fraction of absorbed photons produce an emitted electron. The control gate and the substrate collect the electrons, and the discharge slows as the floating gate potential falls. Reference: R.H. Fowler, Phys. Rev. 38, 45 (1931); D. Frohman-Bentchkowsky, Appl. Phys. Lett. 18, 332 (1971).

Ques: What limits the endurance and retention of an EEPROM?

Each write or erase pushes charge $Q_{p u l se}$ through the window oxide, and the oxide accumulates traps. Trapped electrons in the window oxide reduce the field for the next pulse and close the threshold window, and the traps also raise the leakage (stress-induced leakage current), which shortens retention. The window oxide must be thin (8 to 10 nm) for the voltage to be practical, so these effects cannot be avoided by thicker oxide. The estimate $N_{cy c} \approx Q_{B D} /2 Q_{p u l se}$ is an upper bound, and the usable endurance is smaller because of the window closure. Reference: G. Cappelletti, C. Golla, P. Olivo and E. Zanoni, Flash Memories, Kluwer, 1999.

Ques: What is the relation between MNOS, SNOS and later memory cells?

The metal-nitride-oxide-silicon (MNOS) transistor was an early electrically alterable cell in which a very thin oxide (about 2 nm) lets electrons tunnel directly into traps in the nitride above it. The threshold shift was a function of the logarithm of the pulse time, and the retention was limited by the thin oxide. Polysilicon gates and the SONOS variant improved the reliability, and the later charge trap flash and 3D NAND cells use the same stack idea with a thicker tunnel layer. The floating-gate (FAMOS and EPROM) route is a different concept, in which the charge is stored in a conductor. Reference: H.A.R. Wegener et al., “The variable threshold transistor, a new electrically-alterable, non-destructive read-only storage device,” IEDM, 1967; M.H. White, D.A. Adams and J. Bu, IEEE Circuits Devices Mag. 16(4), 22 (2000).

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