1. Theory

  • Definition: BSIM-CMG (common multi-gate) and BSIM-IMG (independent multi-gate) are Berkeley surface-potential compact models for transistors whose thin, lightly doped body is controlled by more than one gate: CMG for FinFETs, nanowires and other common-gate structures, IMG for back-gated thin-body SOI and independent-gate devices (Lu et al.; BSIM-CMG manual).
  • Undoped-body electrostatics: Because the body is thin and nearly undoped, the Poisson equation is solved for the mobile charge with doping as a perturbation, rather than for the depletion charge of bulk devices (Venugopalan; Lu et al.).
  • Surface-potential core: The surface potentials at source and drain set current and charges, as in PSP, but the implicit equation is solved with a third-order Householder method at a speed similar to BSIM4 (Lu et al.; Surface-Potential Models page).
  • Electrostatic integrity: Short-channel effects scale with a natural length of a few nanometres set by fin thickness and EOT, far shorter than in bulk devices, which is the reason multi-gate devices scale (BSIM-CMG manual; computed).
  • Standard: BSIM-CMG was selected as the industry-standard FinFET model in 2012 (Lu et al.).

2. Working Principle

  • Volume inversion: In a thin body both gates invert the whole film, so carriers are not confined to one surface and the threshold depends on film thickness and doping through a volume-inversion correction (Venugopalan).
  • Geometry: The current scales with the effective width per fin, for a triple gate, times the number of fins, so width is quantized (BSIM-CMG manual; background knowledge for quantization).
  • Short-channel terms: Roll-off and DIBL use hyperbolic-cosine length factors in , with DVT0, DVT1, ETA0 and DSUB carried over from BSIM4 practice (BSIM-CMG manual; BSIM3 and BSIM4 page).
  • Quantum confinement: Below about 20 the inversion charge sits a centroid distance below the interface, which raises the threshold, lowers the effective oxide capacitance and reduces the effective width (Venugopalan; BSIM-CMG manual).
  • Back-gate control: In BSIM-IMG the back gate shifts the front threshold through the series capacitance of film and buried oxide, giving a tuning knob for body biasing (Venugopalan; background knowledge for the coupling form).

3. Applications

  • FinFET and gate-all-around design kits: BSIM-CMG for FinFET nodes and, with the cylindrical and unified geometries, nanowire and nanosheet devices (BSIM-CMG manual; Lu et al.).
  • FD-SOI design kits: BSIM-IMG for ultra-thin-body, thin-BOX FD-SOI with back-gate biasing (Lu et al.).
  • Vertical and pillar transistors: Cylindrical-gate options for vertical FETs, validated on an 80 pillar technology (Venugopalan).
  • Current status: BSIM-CMG is the model in most FinFET and gate-all-around process design kits, while planar bulk processes keep BSIM4 or PSP (background knowledge; BSIM3 and BSIM4 page).

Double-Gate Electrostatics

NameFormulaRelated FormulaeVariables/Constants
Poisson equation of a lightly doped double-gate body










Surface-potential condition and inversion charge







Geometry and Volume Inversion

NameFormulaRelated FormulaeVariables/Constants
Gate geometry and effective width






Volume-inversion threshold correction (cylindrical gate)



Short-Channel and Quantum Effects

NameFormulaRelated FormulaeVariables/Constants
Short-channel roll-off and DIBL in BSIM-CMG







Quantum-mechanical charge centroid







BSIM-IMG

NameFormulaRelated FormulaeVariables/Constants
BSIM-IMG back-gate coupling



Important Questions

Ques: Why can a lightly doped double-gate body be modelled without the depletion charge?

Because in a thin, nearly intrinsic film the fixed charge is small and the mobile electrons dominate the Poisson equation. Venugopalan writes , neglecting holes and fixed charge, which has Taur’s closed-form cosine solution with a parameter set by the boundary condition at the oxide, and then adds doping as a perturbation . The inversion charge is : for his example of a 15 fin with 1.5 oxide, gives electrons per , the charge of about 0.50 of overdrive (computed). Lu et al. solve the implicit equation with a third-order Householder method, which fails only at extreme doping or thickness. Reference: S. Venugopalan, ‘From Poisson to Silicon: Advancing Compact SPICE Models for IC Design’, PhD dissertation, UC Berkeley, Technical Report UCB/EECS-2013-166 (2013) (truncated and partly garbled in the extract) (fetch-tool summary); D. D. Lu, M. V. Dunga, A. M. Niknejad, C. Hu, F.-X. Liang, W.-C. Hung, J.-W. Lee, C.-H. Hsu and M.-H. Chiang, ‘Compact Device Models for FinFET and Beyond’, arXiv:2005.02580 (year not stated, references to 2017) (fetch-tool summary).

Ques: How much stronger is the short-channel control of a FinFET than of a bulk MOSFET?

Much stronger, because the scale length depends on the thin fin. In BSIM-CMG the roll-off length factor is , with set by the permittivity ratio, fin thickness and EOT. With the double-gate form , a 7 fin with 1 EOT has (computed, background knowledge for the form). With assumed DVT0 and DVT1 of 1 and 0.5 of built-in potential difference, the roll-off is 25 at 10 , 1.0 at 20 and 0.05 at 30 (computed). The BSIM3 bulk defaults give a characteristic length of about 60 (BSIM3 and BSIM4 page), almost twenty times longer, which is why bulk devices could not be scaled to 20 gates. Reference: H. Agarwal, P. Kushwaha, A. Dasgupta and M.-Y. Kao (project directors A. Niknejad, S. Salahuddin and C. Hu), ‘BSIM-CMG 111.0.0 Technical Manual’, UC Berkeley (2019) (SIMetrix copy; parameter list not in the excerpt) (fetch-tool summary); BSIM3 and BSIM4 page of this vault.

Ques: How does BSIM-CMG handle quantum confinement in thin fins?

Through a charge-centroid model. The BSIM-CMG manual places the inversion charge at a depth below the interface, so the centroid moves toward the surface as the inversion charge grows. QMFACTOR scales the quantum threshold correction and switches it on, QMTCENIV and QMTCENCV turn on the centroid in current and capacitance, the effective width is reduced, for example by for a triple gate, and the C-V model uses the physical oxide thickness plus the centroid depth. Venugopalan notes that quantum effects dominate for channel diameters below about 20 , and he extracted centroid scales of 12 for a double gate and 6 for a cylindrical gate. Without the centroid, the model would overestimate gate capacitance and current in thin fins (my reading). Reference: H. Agarwal, P. Kushwaha, A. Dasgupta and M.-Y. Kao (project directors A. Niknejad, S. Salahuddin and C. Hu), ‘BSIM-CMG 111.0.0 Technical Manual’, UC Berkeley (2019) (SIMetrix copy; parameter list not in the excerpt) (fetch-tool summary); S. Venugopalan, ‘From Poisson to Silicon: Advancing Compact SPICE Models for IC Design’, PhD dissertation, UC Berkeley, Technical Report UCB/EECS-2013-166 (2013) (truncated and partly garbled in the extract) (fetch-tool summary).

Ques: How does BSIM-CMG describe the width of a FinFET?

As an effective width per fin multiplied by the number of fins. The BSIM-CMG manual gives for a double gate, for a triple gate, for a quadruple gate and for a cylindrical gate, with a trapezoidal option for tapered fins, and the total fin count is NFIN times NF. An assumed fin of 50 height and 7 thickness has 107 per fin as a triple gate, and three fins give 321 , while a 10 nanowire has 31 (computed). Width can therefore be changed only in whole fins, so analog designers size currents in steps (background knowledge). Quantum confinement reduces the effective width further through the centroid term. Device structures are on the FinFET and GAAFET pages. Reference: H. Agarwal, P. Kushwaha, A. Dasgupta and M.-Y. Kao (project directors A. Niknejad, S. Salahuddin and C. Hu), ‘BSIM-CMG 111.0.0 Technical Manual’, UC Berkeley (2019) (SIMetrix copy; parameter list not in the excerpt) (fetch-tool summary); Fin Field Effect Transistor (FinFET) page of this vault; Gate All Around Field Effect Transistor (GAAFET) page of this vault.

Ques: What does BSIM-IMG add for FD-SOI devices?

Independent front and back gates. Lu et al. state that BSIM-IMG covers back-gated ultra-thin-body SOI and independent-gate FinFETs whose front and back gate stacks may be asymmetric, which complicates the surface-potential, current and charge calculations, and that it has been validated against thin-BOX fully-depleted SOI technologies. Venugopalan describes it as modelling an asymmetric double gate with different oxide thicknesses and work functions, treating the back gate as a threshold tuning knob with inversion on one side only. With the simple capacitive coupling , an assumed 7 film, 25 buried oxide and 1 EOT give about 37 of threshold shift per volt of back bias (computed, background knowledge for the form). This back-bias tuning is what FD-SOI uses for adaptive body biasing (background knowledge). Reference: D. D. Lu, M. V. Dunga, A. M. Niknejad, C. Hu, F.-X. Liang, W.-C. Hung, J.-W. Lee, C.-H. Hsu and M.-H. Chiang, ‘Compact Device Models for FinFET and Beyond’, arXiv:2005.02580 (year not stated, references to 2017) (fetch-tool summary); S. Venugopalan, ‘From Poisson to Silicon: Advancing Compact SPICE Models for IC Design’, PhD dissertation, UC Berkeley, Technical Report UCB/EECS-2013-166 (2013) (truncated and partly garbled in the extract) (fetch-tool summary); Silicon on Insulator (SOI) MOSFET page of this vault.

Ques: How accurate and fast are the multi-gate surface-potential models?

Accurate to about 1 to 2 per cent, at about the speed of BSIM4. Venugopalan reports less than 1 per cent rms error after tuning to data and drain-current errors below 2 per cent against TCAD in moderate and strong inversion for radii up to 100 , with tens of microseconds per operating point, validated on TCAD and on a 2.2 vertical cylindrical-gate technology of 80 diameter and 150 height with 3 oxide. Lu et al. state that the computational speed of BSIM-CMG is similar to that of the threshold-based BSIM4, and that the core long-channel model is extended with field-dependent mobility, velocity saturation, a source velocity limit, parasitic resistances and capacitances and leakage currents. The BSIM-CMG manual adds that the model is continuous and symmetric at zero drain voltage. Reference: S. Venugopalan, ‘From Poisson to Silicon: Advancing Compact SPICE Models for IC Design’, PhD dissertation, UC Berkeley, Technical Report UCB/EECS-2013-166 (2013) (truncated and partly garbled in the extract) (fetch-tool summary); D. D. Lu, M. V. Dunga, A. M. Niknejad, C. Hu, F.-X. Liang, W.-C. Hung, J.-W. Lee, C.-H. Hsu and M.-H. Chiang, ‘Compact Device Models for FinFET and Beyond’, arXiv:2005.02580 (year not stated, references to 2017) (fetch-tool summary); H. Agarwal, P. Kushwaha, A. Dasgupta and M.-Y. Kao (project directors A. Niknejad, S. Salahuddin and C. Hu), ‘BSIM-CMG 111.0.0 Technical Manual’, UC Berkeley (2019) (SIMetrix copy; parameter list not in the excerpt) (fetch-tool summary).

Related pages in this vault: BSIM3 and BSIM4, Surface-Potential Models (PSP and HiSIM), Fin Field Effect Transistor (FinFET), Gate All Around Field Effect Transistor (GAAFET), Silicon on Insulator (SOI) MOSFET, Double-Gate MOSFET, Charge-Based Models (EKV), SPICE Level 1-3 MOSFET Models, Tri-Gate MOSFET.