1. Theory
- Definition: The SPICE Level 1, 2 and 3 MOSFET models are the original Berkeley SPICE2 compact models: Level 1 is the square-law model of Shichman and Hodges, Level 2 an analytical model with the bulk charge and most second-order effects, and Level 3 a semi-empirical model fitted to measured data for short channels (Vladimirescu and Liu; Star-Hspice).
- Threshold-voltage basis: All three describe the channel through a threshold voltage with a body effect set by GAMMA and PHI, and treat the drain current as zero below threshold unless a subthreshold option is used (Star-Hspice; Altair).
- Parameter sets: The models share electrical parameters (VTO, KP, GAMMA, PHI, LAMBDA) and process parameters (TOX, NSUB, UO, LD, XJ), and add mobility and velocity-saturation parameters at Level 2 (UCRIT, UEXP, VMAX, NEFF) and THETA, ETA and KAPPA at Level 3 (Altair).
- Range of validity: Level 1 is meant for gate lengths above about 10 and Level 3 down to about 2 ; sub-micrometre devices need BSIM-class models (Patel; Montana EELE 414).
- Capacitances: Gate capacitances follow the Meyer model, which is simple but not charge-conserving (Altair; Pederson).
2. Working Principle
- Square law: Level 1 integrates the inversion charge along the channel with constant mobility, giving the linear and saturation square-law forms, with LAMBDA added empirically for output conductance (Star-Hspice; Long Channel MOSFET page).
- Bulk charge: Level 2 keeps the variation of the depletion charge along the channel, which gives the 3/2-power terms in and a lower current than Level 1 (Patel; background knowledge for the derivation).
- Empirical short-channel terms: Level 3 replaces the bulk-charge terms with a simpler body factor , models drain-induced barrier lowering through ETA, vertical-field mobility reduction through THETA and lateral-field saturation through VMAX, and fits channel-length modulation with KAPPA (Star-Hspice; Patel).
- Parameter hierarchy: When an electrical parameter is not given, SPICE computes it from the process parameters, so the same model card can be physics-based or purely fitted (Altair; Montana EELE 414).
3. Applications
- Hand-calculation checks and teaching: Level 1 for first-order design and checking hand analysis (Vladimirescu and Liu; Montana EELE 414).
- Long-channel and legacy processes: Level 2 and Level 3 for older processes, discrete MOSFETs and large-geometry devices such as power and high-voltage transistors (Patel; background knowledge).
- Fast functional simulation: Simple models where run time matters more than accuracy (Star-Hspice).
- Current status: Modern CMOS processes use BSIM3, BSIM4, BSIM-CMG or PSP model cards, and Levels 1 to 3 remain in simulators mainly for teaching and legacy designs (Montana EELE 414; background knowledge).
Level 1
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Level 1 drain current (Shichman-Hodges) | |||
| Level 1 threshold voltage and process parameters |
Level 2
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Level 2 drain current with bulk charge (Grove-Frohman) | |||
| Level 2 mobility degradation and velocity saturation |
Level 3
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Level 3 drain current and threshold (semi-empirical) | |||
| Level 3 mobility, saturation and channel-length modulation |
Capacitances and Parameters
| Name | Formula | Related Formulae | Variables/Constants |
|---|---|---|---|
| Meyer gate capacitances | |||
| Series resistance and electrical against physical parameters |
Important Questions
Ques: Is the default KP of amperes per square volt consistent with the default mobility and oxide thickness?
Yes. With the SPICE3 defaults listed by Altair, UO = 600 and TOX = 100 , the oxide capacitance is and is (computed), matching the default . The example values in the same table are not mutually consistent, however: UO = 700 would give against the example KP of , and NSUB = with 100 of oxide would give a body coefficient of 1.06 and PHI of 0.67 , not the example 0.37 and 0.65 (computed). The examples are independent illustrations, since explicitly given electrical parameters override those computed from process parameters (my reading). A model card should therefore use one set or the other, as the Montana notes advise. Reference: Altair Activate block reference, SPICE MOSFET element and model parameters (levels 1 to 3), adapted from the SPICE3 user’s manual (fetch-tool summary; some units inferred); Montana State University, EELE 414 Introduction to VLSI Design, Module 3: SPICE Modeling (lecture slides; author and year not stated) (fetch-tool summary).
Ques: Is KP = 40 in the Montana example card in amperes per square volt?
Not as SPICE reads it. The Montana EELE 414 notes give a model card with KP = 40, VT0 = 0.55, GAMMA = 0.34, PHI = 0.3 and LAMBDA = 0.2. SPICE3 defines KP in A/V2, with a default of (Altair), so 40 would mean a transconductance parameter about two million times the default, and an absurd current (computed). The value is most likely meant in microamperes per square volt, as in many textbook tables, and would then be in a real card (my reading). The other values look like a sub-micrometre teaching process: a PHI of 0.3 is low for the surface potential, which would correspond to light doping, and LAMBDA of 0.2 is a strong channel-length modulation for a short device (my reading). In a simulator the unit suffix or scale must match the parameter definition. Reference: Montana State University, EELE 414 Introduction to VLSI Design, Module 3: SPICE Modeling (lecture slides; author and year not stated) (fetch-tool summary); Altair Activate block reference, SPICE MOSFET element and model parameters (levels 1 to 3), adapted from the SPICE3 user’s manual (fetch-tool summary; some units inferred).
Ques: Is SPICE Level 2 or Level 3 the better choice for short-channel devices?
Level 3. Patel’s comparison finds that Level 2 gives lower currents than Level 1 but that the benefit of Level 2 is small, while Level 3, which adds drain-induced barrier lowering through ETA and lateral-field mobility degradation through VMAX, is more efficient mathematically and more accurate, down to about 2 . Star-Hspice describes the same structure: Level 3 replaces Level 2’s 3/2-power bulk-charge terms with a simpler body factor and adds THETA, ETA and KAPPA. Vladimirescu and Liu present Level 2 as analytical and Level 3 as semi-empirical, with parameters fitted to measured data, which is the reason it fits short devices better (my reading). Below about 1 neither is adequate, and BSIM3 is the usual choice, as the Montana notes point out. Reference: T. Patel, ‘Comparison of Level 1, 2 and 3 MOSFET’s’, technical report, University of Texas at Arlington (December 2014) (TI E2E copy; equations garbled in the extract) (fetch-tool summary); Star-Hspice Manual, Release 1998.2, Chapter 16, ‘Selecting a MOSFET Model’ (University of Genoa course copy; equations paraphrased by the fetch tool) (fetch-tool summary); A. Vladimirescu and S. Liu, ‘The Simulation of MOS Integrated Circuits Using SPICE2’, Memorandum UCB/ERL M80/7, University of California, Berkeley (1980) (abstract page only; the PDF could not be fetched); Montana State University, EELE 414 Introduction to VLSI Design, Module 3: SPICE Modeling (lecture slides; author and year not stated) (fetch-tool summary).
Ques: Why did SPICE return to the Meyer capacitance model despite its lack of charge conservation?
Pederson’s report on SPICE development explains that the charge-controlled capacitance model introduced in SPICE2F was not easily applicable to analog circuits at middle and high frequencies, so the default for Levels 2 and 3 went back to the Meyer model, with charge-conserving capacitances still selectable by a parameter. In Meyer’s model, and each equal half of at zero drain voltage and move to two thirds and zero in saturation (computed from the background-knowledge forms). Because these capacitances are not derived from a single charge function, charge is not conserved in transient simulation, which causes errors in charge-sensitive circuits such as switched-capacitor and dynamic logic. Later compact models therefore use charge-based formulations. Altair notes that the Meyer capacitances are included only if TOX is specified. Reference: D. O. Pederson, ‘Continuation of Research in Computer Simulation of Integrated Circuits’, ARO final report, grant DAAG29-81-K-0021 (1984) (DTIC copy) (fetch-tool summary); Altair Activate block reference, SPICE MOSFET element and model parameters (levels 1 to 3), adapted from the SPICE3 user’s manual (fetch-tool summary; some units inferred).
Ques: What limits the accuracy of the Level 1 model?
Its assumptions of constant mobility, constant threshold and no velocity saturation. Patel lists the missing effects: carrier velocity saturation, mobility degradation and weak-inversion conduction, so Level 1 overestimates the current of short devices and is suited to gate lengths above about 10 . Star-Hspice also states that it has no mobility degradation or velocity saturation and recommends it only when speed matters more than accuracy. As an example of its simplicity, a device with KP = , W/L = 10 and 1 of overdrive carries 104 in saturation at 2 with LAMBDA = 0.02 (computed), with the current growing as the square of the overdrive at any length. Vladimirescu and Liu describe it as a first-order model useful for checking hand calculations. Reference: T. Patel, ‘Comparison of Level 1, 2 and 3 MOSFET’s’, technical report, University of Texas at Arlington (December 2014) (TI E2E copy; equations garbled in the extract) (fetch-tool summary); Star-Hspice Manual, Release 1998.2, Chapter 16, ‘Selecting a MOSFET Model’ (University of Genoa course copy; equations paraphrased by the fetch tool) (fetch-tool summary); A. Vladimirescu and S. Liu, ‘The Simulation of MOS Integrated Circuits Using SPICE2’, Memorandum UCB/ERL M80/7, University of California, Berkeley (1980) (abstract page only; the PDF could not be fetched).
Ques: How does THETA describe mobility degradation in Level 3?
As a simple first-order reduction with gate overdrive, (background knowledge for the form). With Altair’s example value of 0.1 , the mobility is 9 per cent lower at 1 of overdrive and 17 per cent lower at 2 (computed), which flattens the square-law rise of current with gate voltage. Star-Hspice adds a second reduction when VMAX is set, through the lateral field, , which also lowers the saturation voltage. Level 3 thereby replaces Level 2’s UCRIT, UEXP and UTRA parameters with a single coefficient, which Patel notes makes it more efficient. THETA absorbs both phonon and surface-roughness effects and the series resistance, so it is a fitting parameter rather than a physical constant (my reading). Reference: Altair Activate block reference, SPICE MOSFET element and model parameters (levels 1 to 3), adapted from the SPICE3 user’s manual (fetch-tool summary; some units inferred); Star-Hspice Manual, Release 1998.2, Chapter 16, ‘Selecting a MOSFET Model’ (University of Genoa course copy; equations paraphrased by the fetch tool) (fetch-tool summary); T. Patel, ‘Comparison of Level 1, 2 and 3 MOSFET’s’, technical report, University of Texas at Arlington (December 2014) (TI E2E copy; equations garbled in the extract) (fetch-tool summary).
Related pages in this vault: Charge-Based Models (EKV), Surface-Potential Models (PSP and HiSIM), Long Channel MOSFET, Charge and Capacitance Modelling, Multi-Gate Models (BSIM-CMG and BSIM-IMG), BSIM3 and BSIM4, Short Channel MOSFET, Power Device Compact Models, Diode Compact Models.