Dynamic Random Access Memory (DRAM)

1. Theory

• Definition: Dynamic random access memory (DRAM) stores each bit as charge on a small capacitor reached through a single access transistor (the 1T1C cell).
• Dynamic storage: No feedback holds the charge, so it leaks away and must be refreshed periodically.
• Storage capacitor: Kept near 10–25 fF across generations by making capacitors taller and using high-k dielectrics (e.g. $\mathrm{Zr}{\mathrm{O}}_2/A{\mathrm{l}}_2{\mathrm{O}}_3/Zr{\mathrm{O}}_2$).
• Capacitor evolution: Planar, then trench and stacked, and now tall cylindrical metal-insulator-metal capacitors with aspect ratios of several tens.
• Access transistor: Needs an extremely low off-current (femtoamperes), so it uses a high threshold and a recessed or buried channel.
• Cell area: $8F^2$ (folded bitline) or $6F^2$ (open bitline); $4F^2$ requires a vertical access transistor.

2. Working Principle

• Write: The wordline turns on the access transistor and the bitline charges or discharges the capacitor; a boosted wordline ($V_{PP}\ge V_{DD}+V_{TH}$) stores a full high level.
• Read by charge sharing: The capacitor shares its charge with the much larger bitline capacitance, giving a small signal $\Delta V_{BL}\approx \pm (V_{DD}/2)C_s/(C_s+C_{BL})$.
• Destructive read: Charge sharing destroys the stored value, so the sense amplifier writes it back after every read.
• Leakage paths: Subthreshold current, junction generation, gate-induced drain leakage (GIDL) and capacitor dielectric leakage drain the cell.
• Retention and refresh: Retention time $t_{ret}=C_s\Delta V_{max}/I_{leak}$; refresh must cover the weakest cell in the tail of the distribution.
• Temperature: Leakage is thermally activated, so retention falls sharply at high temperature.

3. Applications

• Main memory: DDR system memory in PCs, servers and data centres.
• Mobile memory: LPDDR in smartphones, tablets and laptops.
• Graphics and AI memory: GDDR on graphics cards and stacked HBM beside GPUs and AI accelerators.

Name	Formula	Related Formulae	Variables/Constants
Stored charge and number of electrons	$Q_s=C_s{V}_s$ $N_e=\frac{Q_s}{q}$	$Q_{sig}=C_s\left(V_s-V_{pre}\right)$	$Q_s:chargestoredonthecellcapacitor$ $C_s:storagecapacitance$ $\begin{array}{r}{V}_s:voltageonthestoragenode(V_{DD}\\ fora1and0Vfora0)relativeto\\ theplate\end{array}$ $N_e:numberofelectronsrepresentingthesignal$ $\begin{array}{r}{V}_{pre}:prechargevoltageofthe\\ bitline,usually{V}_{DD}/2\end{array}$ $\begin{array}{r}{Q}_{sig}:signalchargethatisreleased\\ ontothebitlineduringaread\end{array}$
Storage capacitance and equivalent oxide thickness	$C_s=\frac{{\epsilon }_0{\epsilon }_{r}A}{t_{phys}}=\frac{{\epsilon }_0{\epsilon }_{Si{O}_2}A}{EOT}$	$EOT={\sum }_i{t}_i\frac{{\epsilon }_{Si{O}_2}}{{\epsilon }_{r,i}}$ $EOT=t_{phys}\frac{3.9}{{\epsilon }_r}$	$\begin{array}{r}{\epsilon }_r:relativepermittivityof\\ thecapacitordielectric\end{array}$ $A:electrodeareaofthecapacitor$ $t_{phys}:physicalthicknessofthedielectric$ $\begin{array}{r}EOT:equivalentoxidethickness,the\\ Si{O}_{2}thicknessthatgivesthesame\\ capacitance\end{array}$ $\begin{array}{r}{t}_i,{\epsilon }_{r,i}:thicknessand\\ relativepermittivityoflayeriina\\ stackeddielectricsuchas\\ Zr{O}_2/A{l}_2{O}_3/Zr{O}_2\end{array}$ $\begin{array}{r}(metalelectrodesassumed,sothereis\\ nodepletionorquantumcapacitance\\ correction)\end{array}$
Capacitor area of a cylindrical electrode	$A\approx \pi dh=\pi AR{d}^2$	$AR=\frac{h}{d}$ $C_s\approx \frac{{\epsilon }_0{\epsilon }_r\pi AR{d}^2}{t_{phys}}$	$\begin{array}{r}A:areaofonesidewallofthe\\ cylindrical(cuporpillar)electrode,\\ withthebottomareaneglected\end{array}$ $d:diameteroftheelectrode$ $h:heightoftheelectrode$ $\begin{array}{r}AR:aspectratiooftheelectrode,which\\ growsasdshrinkstohold{C}_{s}constant\end{array}$ $\begin{array}{r}(usingboththeinnerandouterwallof\\ acuproughlydoublesA)\end{array}$
Stored 1 level with an NMOS access transistor	$V_s=\min \left[V_{DD},V_{WL}-V_{TH}\left(V_{SB}\right)\right]$	$V_{TH}\left(V_{SB}\right)=V_{TH0}+\gamma \left(\sqrt{2{\varphi }_F+V_{SB}}-\sqrt{2{\varphi }_F}\right)$ $V_{PP}\ge V_{DD}+V_{TH}\left(V_{DD}\right)$	$V_{WL}:wordlinehighvoltage$ $\begin{array}{r}{V}_{TH}(V_{SB}):thresholdvoltageofthe\\ accesstransistorwithsource-bodyvoltage\\ V_{SB},whichequalsthestoredvoltage\end{array}$ $V_{TH0}:thresholdvoltageatzerosource-bodybias$ $\gamma :bodyeffectcoefficient$ ${\varphi }_F:Fermipotentialofthebody$ $\begin{array}{r}{V}_{PP}:boostedwordlinevoltagethat\\ allowsthefull{V}_{DD}tobewritten\\ intothecell\end{array}$
Read signal (charge sharing)	$\Delta V_{BL}=\left(V_s-V_{pre}\right)\frac{C_s}{C_s+C_{BL}}$	$\Delta V_{BL}=\pm \frac{V_{DD}}{2}\frac{C_s}{C_s+C_{BL}}(V_{pre}=V_{DD}/2)$ $V_{BL}^{final}=\frac{C_s{V}_s+C_{BL}{V}_{pre}}{C_s+C_{BL}}$	$\begin{array}{r}\Delta V_{BL}:changeofthebitline\\ voltageafterthewordlineturnson\end{array}$ $\begin{array}{r}{C}_{BL}:capacitanceofthebitline,\\ usuallyseveraltimeslargerthan{C}_s\end{array}$ $\begin{array}{r}{V}_{BL}^{final}:commonvoltageofthe\\ bitlineandthecellaftercharge\\ sharing\end{array}$ $\begin{array}{r}(thesignispositiveforastored1\\ andnegativeforastored0,anda\\ readdestroysthestoredvalue,soit\\ mustberewritten)\end{array}$
Write time	$t_w=R_{on}{C}_s\ln \frac{1}{ϵ}$	$R_{on}=\frac{L}{{\mu }_n{C}_{ox}W\left(V_{GS}-V_{TH}\right)}$	$\begin{array}{r}{t}_w:timetochargethecapacitorto\\ withinafractionϵofthefinal\\ value\end{array}$ $\begin{array}{r}{R}_{on}:on-resistanceoftheaccess\\ transistorinthelinearregion\end{array}$ $\begin{array}{r}L,W:channellengthandwidthofthe\\ accesstransistor\end{array}$ $\begin{array}{r}{\mu }_n,C_{ox}:electronmobilityandgate\\ oxidecapacitanceperunitarea\end{array}$ $V_{GS}-V_{TH}:gateoverdrive$ $\begin{array}{r}(thebitlineresistanceandcapacitance\\ addfurtherdelay)\end{array}$ $\begin{array}{r}(constant{R}_{on}isoptimistic:asthe\\ nodechargestowarda1,V_{GS}fallsand\\ V_{TH}risesbythebodyeffect,sothe\\ finalapproachisslowerthanRC;the\\ boosted{V}_{PP}keepstheoverdriveup)\end{array}$
Retention time and the allowed off-current	$t_{ret}=\frac{C_s\Delta V_{max}}{I_{leak}}$	$I_{leak,max}=\frac{C_s\Delta V_{max}}{t_{REF}}$ $t_{ret}\ge t_{REF}$	$\begin{array}{r}{t}_{ret}:timeforthestoredchargeto\\ leakawayuntilthesignalisnolonger\\ readable\end{array}$ $\begin{array}{r}\Delta V_{max}:largesttolerabledropof\\ thestored1level\end{array}$ $\begin{array}{r}{I}_{leak}:totalleakageofthestorage\\ node,takenasconstant\end{array}$ $\begin{array}{r}{t}_{REF}:refreshinterval(64msator\\ below85{}^{\circ }CinDDR3andDDR4,halved\\ above85{}^{\circ }C;DDR5uses32ms)\end{array}$ $\begin{array}{r}{I}_{leak,max}:leakagethatthecellcan\\ tolerateforagivenrefreshinterval,\\ oftheorderoffemtoamperes\end{array}$
Leakage components of the storage node	$I_{leak}=I_{sub}+I_{gen}+I_{GIDL}+I_{cap}$	$I_{sub}=I_0\frac{W}{L}{e}^{\left(V_{GS}-V_{TH}\right)/n{\varphi }_t}\left(1-e^{-V_{DS}/{\varphi }_t}\right)$	$\begin{array}{r}{I}_{sub}:subthresholdleakagethroughthe\\ offaccesstransistor\end{array}$ $\begin{array}{r}{I}_{gen}:generationcurrentofthe\\ reverse-biasedstoragenodejunction\end{array}$ $\begin{array}{r}{I}_{GIDL}:gate-induceddrainleakageat\\ thegateedgeoverthestoragejunction\end{array}$ $I_{cap}:leakagethroughthecapacitordielectric$ $I_0:technology-dependentprefactor$ $n:subthresholdslopefactor$ ${\varphi }_t:thermalvoltage{k}_{B}T/q$ $\begin{array}{r}(thewordlineofanoffcellisoften\\ heldslightlynegativetocut{I}_{sub}\\ andthisincreases{I}_{GIDL})\end{array}$ $k_B:Boltzmannconstant$
Junction generation leakage	$I_{gen}=\frac{q{n}_i{W}_{dep}{A}_j}{2{\tau }_g}$	$W_{dep}=\sqrt{\frac{2{\epsilon }_s\left(V_{bi}+V_R\right)}{q{N}_{sub}}}$ $I_{gen}\propto \sqrt{V_{bi}+V_R}$	$\begin{array}{r}{I}_{gen}:Shockley-Read-Hallgeneration\\ currentinthedepletionregionofthe\\ storagejunction\end{array}$ $n_i:intrinsiccarrierconcentration$ $W_{dep}:depletionwidthofthejunction$ $A_j:junctionarea$ ${\tau }_g:generationlifetime$ $\begin{array}{r}{V}_{bi},V_R:built-involtageandreverse\\ biasofthejunction\end{array}$ $N_{sub}:dopingofthelightlydopedside$ $\begin{array}{r}(SRHgenerationonly;theweakcellsin\\ theretentiontailareusuallylimitedby\\ field-enhancedgeneration(trap-assisted\\ tunnelling,Poole-Frenkelloweringofthe\\ trapemissionbarrier),whichreducesthe\\ effective{\tau }_{g}inhigh-fieldspots)\end{array}$
Gate-induced drain leakage	$I_{GIDL}=A_g{E}_s{e}^{-B_g/E_s}$	$E_s\approx \frac{V_{DG}-1.2\mathrm{V}}{3T_{ox}}$	$\begin{array}{r}{I}_{GIDL}:band-to-bandtunnellingcurrent\\ inthedrainregionthatoverlapsthe\\ gate\end{array}$ $\begin{array}{r}{E}_s:surfaceelectricfieldatthe\\ gate-drainoverlap\end{array}$ $\begin{array}{r}{A}_g,B_g:fittingconstants,with{B}_g\\ relatedtothebandgapandeffective\\ mass\end{array}$ $V_{DG}:drain-to-gatevoltage$ $T_{ox}:gateoxidethickness$ $\begin{array}{r}(Chanetal.empiricalmodel:1.2Vis\\ thebandbending,about{E}_g/q,needed\\ beforeband-to-bandtunnellingstarts,\\ and3\approx {\epsilon }_{Si}/{\epsilon }_{ox}convertsthe\\ oxidefieldintothesiliconsurfacefield;\\ BSIMusesthesameformwithafitted\\ voltageoffset)\end{array}$
Temperature dependence of retention	$t_{ret}(T)=t_{ret}\left(T_0\right)\exp \left[\frac{E_a}{k_B}\left(\frac{1}{T}-\frac{1}{T_0}\right)\right]$	$E_a\approx \frac{E_g}{2}\text{(generation limited)}$	$t_{ret}(T):retentiontimeattemperatureT$ $T_0:referencetemperature$ $\begin{array}{r}{E}_a:activationenergyofthedominant\\ leakagepath\end{array}$ $E_g:bandgapofthesemiconductor$ $\begin{array}{r}(subthresholdleakagehasadifferent,\\ gate-dependentactivationenergy,sothe\\ slopechangeswiththedominantpath;\\ tailcellswithfield-enhanced\\ generationshowalower{E}_{a}than{E}_g/2)\end{array}$ $k_B:Boltzmannconstant$
Capacitor dielectric leakage	$J_{SE}=A^{\ast }{T}^2\exp \left[-\frac{q\left({\Phi }_B-\sqrt{qE/4\pi {\epsilon }_i}\right)}{k_{B}T}\right]$	$J_{PF}=q\mu N_{C}E\exp \left[-\frac{q\left({\Phi }_T-\sqrt{qE/\pi {\epsilon }_i}\right)}{k_{B}T}\right]$ $E=\frac{V_{cap}}{t_{phys}}$	$\begin{array}{r}{J}_{SE}:Schottkyemissioncurrentdensity\\ overtheelectrode-dielectricbarrier\end{array}$ $\begin{array}{r}{J}_{PF}:Poole-Frenkelcurrentdensityfrom\\ trapstatesinthedielectric\end{array}$ $A^{\ast }:effectiveRichardsonconstant$ $\begin{array}{r}{\Phi }_B,{\Phi }_T:barrierheightandtrap\\ depthinvolts\end{array}$ $\begin{array}{r}{\epsilon }_i:high-frequency(optical)\\ permittivityofthedielectric\end{array}$ $\begin{array}{r}\mu ,N_C:electronmobilityandeffective\\ densityofstatesofthedielectric\\ conductionband\end{array}$ $\begin{array}{r}E:electricfieldinthedielectric,\\ with{V}_{cap}thevoltageacrossit\end{array}$ $\begin{array}{r}(theleakageincreasesasEOTisreduced\\ forthesamevoltage;inZr{O}_2-basedstacks\\ trap-assistedtunnellingoftendominates\\ atlowfield)\end{array}$ $k_B:Boltzmannconstant$
Cell area	$A_{cell}=a{F}^2$	$a=6\text{(open bitline)}$ $a=8\text{(folded bitline)}$	$A_{cell}:areaofoneDRAMcell$ $F:minimumfeaturesize$ $\begin{array}{r}a:cellareafactor:bitlinepitchtimes\\ celllengthalongthebitline,2F\times 4F\\ forthefolded8F^{2}celland3F\times 2Ffor\\ theopen6F^{2}cell\end{array}$

Important Questions

Ques: Why is DRAM called dynamic, and what does a single transistor and capacitor store?

A DRAM cell stores one bit as charge on a small capacitor $C_s$ and uses one NMOS access transistor to connect it to the bitline. The charge $Q_s=C_s{V}_s$ is not held by any feedback, so it leaks away through the access transistor, the storage node junction and the dielectric, and it must be restored before $t_{ret}=C_s\Delta V_{max}/I_{leak}$ has elapsed. This periodic restoring is called refresh. Because a read shares the charge with the much larger bitline capacitance, it destroys the stored value, so every read is followed by a write-back. Reference: B. Prince, Semiconductor Memories, 2nd ed., Wiley, 1991.

Ques: How large does the storage capacitance have to be, and why has it stayed near 10 to 25 fF?

The read signal $\Delta V_{BL}=\pm (V_{DD}/2)C_s/(C_s+C_{BL})$ must exceed the sense offset, noise and leakage loss, which sets a lower limit on $C_s/C_{BL}$. A smaller capacitor also holds fewer electrons ($N_e=C_s{V}_s/q$ is only tens of thousands), so it is more sensitive to charge from alpha particles and neutrons. As the feature size $F$ shrinks by about 0.7 per generation (so the cell area roughly halves), the capacitor was given more height and a thinner, higher-permittivity dielectric to keep $C_s$ roughly constant, instead of reducing it. Reference: Kinam Kim, “Technology for sub-50nm DRAM and NAND flash manufacturing,” IEDM Tech. Dig., 323 (2005); US patent application 2007/0217245, “6F2 DRAM cell design with 3F-pitch folded digitline sense amplifier” (3F by 2F cell).

Ques: Why does the access transistor need a boosted wordline and an extremely low off-current?

An NMOS transistor passes a high level only up to $V_{WL}-V_{TH}(V_{SB})$, and the body effect raises the threshold as the source rises, so the wordline is boosted to $V_{PP}\ge V_{DD}+V_{TH}(V_{DD})$ to store the full level. In the off state the transistor must leak less than $I_{leak,max}=C_s\Delta V_{max}/t_{REF}$, which is only a few femtoamperes. This is far below the leakage of a logic transistor, so the access device uses a higher threshold, a low-doped storage node, and a long effective channel that is folded into the substrate (recessed or buried-channel array transistors), which keeps the cell footprint small without increasing short-channel leakage. Reference: S.M. Sze and Kwok K. Ng, Physics of Semiconductor Devices, 3rd ed., Wiley, 2007.

Ques: What sets the retention time, and why is the worst cell more important than the average?

The retention time is determined by the sum of the leakage paths: subthreshold current, junction generation (which has an activation energy near $E_g/2$), GIDL at the gate edge, and capacitor leakage. The electric field at the storage junction is the key variable, because it raises both the trap-assisted generation and the GIDL. The distribution of retention times across billions of cells has a long tail of weak cells with a defect near the junction, and some of these show variable retention time: a defect near the junction switches at random between two configurations with different generation rates, so the same cell toggles between a long and a short retention time, which makes the weakest cells hard to screen. The refresh interval must cover the weakest cell, so the tail, rather than the median, determines the refresh rate. Reference: T. Hamamoto, S. Sugiura and S. Sawada, “On the retention time distribution of dynamic random access memory (DRAM),” IEEE Trans. Electron Devices 45, 1300 (1998); P.J. Restle, J.W. Park and B.F. Lloyd, “DRAM variable retention time,” IEDM Tech. Dig., 807 (1992); T.Y. Chan, J. Chen, P.K. Ko and C. Hu, “The impact of gate-induced drain leakage current on MOSFET scaling,” IEDM Tech. Dig., 1987, p. 718.

Ques: How did the capacitor structure and dielectric change as cells shrank?

Early cells used a planar capacitor on the silicon surface. Trench capacitors etched into the substrate and stacked capacitors above the transistor then gave a larger area for the same footprint. Modern cells use tall cylindrical metal-insulator-metal capacitors, with TiN electrodes and aspect ratios of several tens, so $A\approx \pi AR{d}^2$ is large even for a small diameter. The dielectric moved from SiO${}_2$/Si${}_3$N${}_4$ to Ta${}_2$O${}_5$, then to Al${}_2$O${}_3$ and HfO${}_2$/Al${}_2$O${}_3$, and to ZrO${}_2$-based stacks such as ZrO${}_2$/Al${}_2$O${}_3$/ZrO${}_2$, which give a low EOT while the thin Al${}_2$O${}_3$ layer blocks leakage. The limit now is the mechanical stability of tall electrodes and the leakage at an EOT well below 1 nm. Reference: Kinam Kim, IEDM Tech. Dig., 2005; S.M. Sze and Kwok K. Ng, Physics of Semiconductor Devices, 3rd ed., Wiley, 2007.

Ques: What are the 6F² and 8F² cells?

The cell area is $A_{cell}=a{F}^2$, where $F$ is the minimum feature size. In the folded layout the bitline pitch is 2F, and each cell is 4F long along the bitline, because each wordline crosses both bitlines of a pair but contacts a cell on only one of them, so a passing wordline runs through every cell; this gives $2F\times 4F=8F^2$. The open-bitline layout puts the reference bitline in a neighbouring array, so the passing wordline goes and the cell is only 2F long; the bitline pitch is relaxed to 3F, giving $3F\times 2F=6F^2$. The price is poorer noise cancellation, since the two bitlines of a sense amplifier no longer run side by side. Further reduction to $4F^2$ requires a vertical access transistor beneath the capacitor. Reference: B. Prince, Semiconductor Memories, 2nd ed., Wiley, 1991; Kinam Kim, “Technology for sub-50nm DRAM and NAND flash manufacturing,” IEDM Tech. Dig., 323 (2005).

Related pages in this vault: Gain Cell (2T and 3T eDRAM), Static Random Access Memory (SRAM), Floating Body Random Access Memory (Capacitorless 1T DRAM), Static and Dynamic Random Access Memory (SRAM and DRAM), Ferroelectric NAND and 3D Ferroelectric Memory (Vertical FeFET and Stacked FeRAM), Ferroelectric Random Access Memory (FeRAM), Deep-Trench Capacitors.