Gate All Around Field Effect Transistor (GAAFET)

1. Theory

• Definition: A gate-all-around FET (GAAFET) is a transistor in which the gate completely surrounds the channel on all sides.
• Scope: This page covers the cylindrical nanowire, the stacked rectangular nanosheet, and two architecture variants built on nanosheet physics, the forksheet and the complementary FET (CFET).
• Limit of the multi-gate series: A rectangular body has $N=4$ effective gates, compared with $N=2$ for the double gate and $N=3$ for the tri-gate, giving the shortest natural length.
• Nanowire: A cylindrical channel with perimeter $\pi D$ gives excellent electrostatics but little current per wire.
• Nanosheet: Wide, thin sheets stacked vertically give a gated width of about $2W_{NS}$ per sheet, and the sheet width can be chosen continuously rather than in fin steps.
• Undoped channel: The threshold is set by the gate work function, with quantum confinement adding a shift that grows as the sheet or wire is thinned.

2. Working Principle

• All-around gate control: The gate shields the channel from the drain on every side, giving the strongest suppression of DIBL and roll-off and allowing the shortest gate lengths.
• Stacked drive current: Several sheets conduct in parallel, multiplying drive current per unit footprint.
• Stack limits: Sheet spacing must leave room for gate oxide and work-function metal on both faces; taller stacks add parasitic capacitance and process difficulty.
• Near-ideal swing: Long-channel devices approach 60 mV/dec.
• Forksheet: A dielectric wall between n- and p-type sheets lets them sit closer together, at the cost of one ungated edge (three-gate electrostatics).
• CFET: n- and p-type devices stacked on top of each other roughly halve the logic cell footprint in the ideal limit.
• Variability: Threshold sensitivity to sheet thickness grows as $1/T_{NS}^3$, so thickness control is critical.

3. Applications

• Leading-edge logic at the 3 nm and 2 nm class: Nanosheet GAA transistors in the newest CPUs, mobile processors and AI accelerators.
• Future scaling roadmap: Forksheet and CFET are being developed for nodes beyond nanosheets (research and development stage).

Nanowire (cylindrical) GAA

Name	Formula	Related Formulae	Variables/Constants
Cylindrical gate capacitance per unit length	$C^{\prime }=\frac{2\pi {\epsilon }_{ox}}{\ln \left(1+t_{ox}/R\right)}$	$\begin{array}{r}{C}^{\prime }\to \frac{2\pi R{\epsilon }_{ox}}{t_{ox}}(t_{ox}\ll R)\\ \text{(planar limit)}\end{array}$	$\begin{array}{r}{C}^{\prime }:\text{gate capacitance per unit wire length}\\ \text{(coaxial capacitor)}\end{array}$ $\begin{array}{r}R:\text{silicon wire radius},D=2R\\ t_{ox}:\text{gate oxide thickness}\end{array}$
Effective width	$W_{eff}=2\pi R=\pi D$	$W_{total}=N_{NW}\pi D$	$\begin{array}{r}{W}_{eff}:\text{perimeter of the wire}\\ N_{NW}:\text{number of wires in parallel}\end{array}$
Natural length (cylindrical GAA)	${\lambda }_{cyl}=\sqrt{\frac{2{\epsilon }_s{D}^2\ln \left(1+2t_{ox}/D\right)+{\epsilon }_{ox}{D}^2}{16{\epsilon }_{ox}}}$	$\begin{array}{r}{\lambda }_{cyl}\approx \sqrt{\frac{{\epsilon }_s}{4{\epsilon }_{ox}}D{t}_{ox}}(D/12\ll t_{ox}\ll D)\\ {\lambda }_{cyl}\to \frac{D}{4}(t_{ox}\to 0)\end{array}$	$\begin{array}{r}{\lambda }_{cyl}:\text{natural length of the surrounding-gate}\\ \text{wire}\end{array}$ $\begin{array}{r}\text{(the thin-oxide limit equals}{\lambda }_N\text{with}N=4\text{)}\end{array}$
Short-channel behavior and gate-length rule	$\Delta V_{TH},{\eta }_{DIBL}\propto \exp \left(-\frac{L}{2{\lambda }_{cyl}}\right)$	$\begin{array}{r}L\gtrsim 5\text{to}6{\lambda }_{cyl}\text{(rule of thumb)}\\ \text{(see Double-Gate MOSFET page)}\end{array}$	$\begin{array}{r}\text{(same form as the double-gate page; the}\\ \text{shorter}{\lambda }_{cyl}\text{allows shorter gates)}\end{array}$
Radial quantum confinement	$E_1=\frac{j_{0,1}^2{\hslash }^2}{2m^{\ast }{R}^2},j_{0,1}\approx 2.405$	$\Delta V_{TH}\approx \frac{E_1}{q}$	$\begin{array}{r}{E}_1:\text{lowest subband energy of the}\\ \text{circular cross-section}\end{array}$ $\begin{array}{r}{j}_{0,1}:\text{first zero of the Bessel function}{J}_0\end{array}$ $\begin{array}{r}\text{(threshold rises as}{R}^{-2}\text{when the wire is}\\ \text{thinned)}\end{array}$
Drain current (long channel)	$I_D={\mu }_n\frac{C^{\prime }}{L}\left[\left(V_{GS}-V_{TH}\right)V_{DS}-\frac{V_{DS}^2}{2}\right]$	$\begin{array}{r}{I}_{Dsat}=\frac{{\mu }_n{C}^{\prime }}{2L}{\left(V_{GS}-V_{TH}\right)}^2\\ \text{(see Long Channel MOSFET page)}\end{array}$	$\begin{array}{r}\text{(the product}{C}_{ox}Z\text{of the planar expression}\\ \text{is replaced by}{C}^{\prime }\text{per wire; multiply by}{N}_{NW}\\ \text{for parallel wires)}\end{array}$
Ideal long-channel subthreshold swing	$S\to \ln (10)\frac{k_{B}T}{q}\approx 60mV/dec$	$\begin{array}{r}L\gg {\lambda }_{cyl}\\ \text{(see Double-Gate MOSFET page)}\end{array}$	$\begin{array}{r}\text{(no depletion-capacitance divider in an}\\ \text{undoped wire)}\end{array}$ $k_B:Boltzmannconstant$

Nanosheet GAA

Name	Formula	Related Formulae	Variables/Constants
Effective width per sheet	$W_{eff,sheet}=2\left(W_{NS}+T_{NS}\right)$	$\begin{array}{r}{W}_{eff,sheet}\approx 2W_{NS}(W_{NS}\gg T_{NS})\\ \text{(see Tri-Gate MOSFET page for the perimeter idea)}\end{array}$	$\begin{array}{r}{W}_{NS}:\text{sheet width}\\ T_{NS}:\text{sheet thickness}\end{array}$ $\begin{array}{r}\text{(a wide sheet is gated mainly on its}\\ \text{top and bottom faces)}\end{array}$
Stack effective width and footprint gain	$W_{eff,stack}=N_{sheet}\cdot 2\left(W_{NS}+T_{NS}\right)$	$G_W=\frac{W_{eff,stack}}{W_{NS}}\approx 2N_{sheet}$	$\begin{array}{r}{N}_{sheet}:\text{number of stacked sheets}\\ G_W:\text{gated width per unit footprint width}\end{array}$ $\begin{array}{r}\text{(sheet}\text{width}\text{can}\text{be}\text{chosen}\text{continuously,}\\ \text{unlike}\text{the}\text{integer}\text{fin}\text{count}\text{of}\text{the}\text{FinFET}\\ \text{page)}\end{array}$
Stack height and sheet spacing	$H_{stack}=N_{sheet}{T}_{NS}+\left(N_{sheet}-1\right)S_{NS}$	$S_{NS}\gtrsim 2\left(t_{ox}+t_m\right)$	$\begin{array}{r}{S}_{NS}:\text{vertical spacing between sheets}\\ t_m:\text{work-function metal thickness}\end{array}$ $\begin{array}{r}\text{(the gap between sheets must hold the gate}\\ \text{oxide and metal on both facing surfaces)}\end{array}$
Natural length (rectangular GAA)	${\lambda }_{NS}={\left[\frac{2{\epsilon }_{ox}}{{\epsilon }_s{t}_{ox}}\left(\frac{1}{W_{NS}}+\frac{1}{T_{NS}}\right)\right]}^{-1/2}$	$\begin{array}{r}{\lambda }_N=\sqrt{\frac{{\epsilon }_s}{N{\epsilon }_{ox}}{t}_{Si}{t}_{ox}}\\ N=4\text{for}{W}_{NS}=T_{NS}=t_{Si}\end{array}$	$\begin{array}{r}\text{(approximate, thin-oxide limit: the}\\ \text{inverse squares of the two directions}\\ \text{are added; compare the Tri-Gate}\\ \text{MOSFET page)}\end{array}$ $\begin{array}{r}\text{(for}{W}_{NS}\gg T_{NS}\text{the sheet behaves}\\ \text{like a double gate across}{T}_{NS}\text{)}\end{array}$
Two-dimensional quantum confinement	$E_{11}=\frac{{\pi }^2{\hslash }^2}{2m^{\ast }}\left(\frac{1}{W_{NS}^2}+\frac{1}{T_{NS}^2}\right)$	$\frac{d{V}_{TH}}{d{T}_{NS}}\approx -\frac{{\pi }^2{\hslash }^2}{q{m}^{\ast }{T}_{NS}^3}$	$\begin{array}{r}{E}_{11}:\text{lowest subband energy of the sheet}\\ \text{(infinite-well approximation)}\end{array}$ $\begin{array}{r}\text{(for a wide sheet the thickness term}\\ \text{dominates; see the Tri-Gate MOSFET and}\\ \text{Fin Field-Effect Transistor pages)}\end{array}$
Drain current of the stack	$I_{Dsat}=N_{sheet}\frac{{\mu }_n{C}_{ox}}{2m}\frac{W_{eff,sheet}}{L}{\left(V_{GS}-V_{TH}\right)}^2$	$\begin{array}{r}m\approx 1\\ \text{(see Long Channel MOSFET page)}\end{array}$	$\begin{array}{r}\text{(for a single fin or wire replace}\\ W_{eff,sheet}\text{by its perimeter)}\end{array}$

Forksheet and CFET (architecture variants)

Name	Formula	Related Formulae	Variables/Constants
Forksheet effective width per sheet	$W_{eff,fork}=2W_{NS}+T_{NS}$	$\begin{array}{r}{W}_{eff,sheet}=2W_{NS}+2T_{NS}\\ \text{(full nanosheet, for comparison)}\end{array}$	$\begin{array}{r}\text{(the edge of the sheet that faces the}\\ \text{dielectric wall between the n and p devices}\\ \text{is not gated)}\end{array}$
Forksheet natural length	${\lambda }_{fork}={\left[\frac{{\epsilon }_{ox}}{{\epsilon }_s{t}_{ox}}\left(\frac{2}{T_{NS}}+\frac{1}{W_{NS}}\right)\right]}^{-1/2}$	$\begin{array}{r}\text{(top and bottom faces act as a double gate across}{T}_{NS}\text{;}\\ \text{one edge acts as a single gate across}{W}_{NS}\text{)}\end{array}$	$\begin{array}{r}\text{(approximate, thin-oxide limit; the}\\ \text{three-gated structure lies between the}\\ \text{double-gate and full nanosheet values)}\end{array}$
CFET stack height	$H_{CFET}=H_n+t_{sep}+H_p$	$H_{n,p}=N_{sheet}{T}_{NS}+\left(N_{sheet}-1\right)S_{NS}$	$\begin{array}{r}{H}_n,H_p:\text{heights of the n-type and p-type}\\ \text{sheet stacks}\end{array}$ $\begin{array}{r}{t}_{sep}:\text{isolation (separation) layer}\\ \text{between the two stacks}\end{array}$
CFET footprint (ideal limit)	$A_{CFET}\approx \frac{A_{pair}}{2}$	$\begin{array}{r}{A}_{pair}\approx 2A_{FET}\\ \text{(n and p side by side)}\end{array}$	$\begin{array}{r}{A}_{CFET}:\text{layout area of a stacked n-p pair}\\ A_{pair}:\text{area when the n and p devices}\\ \text{are placed side by side}\end{array}$ $\begin{array}{r}\text{(an ideal bound; contacts and routing}\\ \text{reduce the actual gain)}\end{array}$

Important Questions

Ques: Why does gate-all-around give the best electrostatic control, and what do the formulas show?

Each additional gated face shields the channel further from the drain, and this appears directly in the natural length. For a rectangular body the effective number of gates rises from $N=2$ (double gate) to $N=3$ (tri-gate) to $N=4$ (gate-all-around), shortening ${\lambda }_N=\sqrt{{\epsilon }_s{t}_{Si}{t}_{ox}/(N{\epsilon }_{ox})}$ accordingly. For the cylindrical wire the same limit holds, ${\lambda }_{cyl}\approx \sqrt{{\epsilon }_{s}D{t}_{ox}/(4{\epsilon }_{ox})}$ (for $D/12\ll t_{ox}\ll D$), and for a vanishing oxide the exact form tends toward $D/4$ (the exact Laplace solution gives $D/4.81$), so the best that can be achieved is set by the wire diameter alone. Since threshold roll-off and DIBL fall as $\exp (-L/2\lambda )$, a gate-all-around device can use a shorter gate for the same short-channel behavior. Reference: C.P. Auth and J.D. Plummer, “Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET’s,” IEEE Electron Device Lett. 18, 74 (1997); J.-P. Colinge, FinFETs and Other Multi-Gate Transistors, Springer, 2008.

Ques: Why did the industry move from nanowires to nanosheets?

A single nanowire gives excellent electrostatics but its perimeter $\pi D$ is small, so many wires would be needed to supply useful current, and the footprint per amp of drive current becomes poor. A nanosheet has the same all-around gate but is wide, so its perimeter is dominated by the two broad faces, $W_{eff,sheet}\approx 2W_{NS}$, and stacking $N_{sheet}$ of them gives a gated width of about $2N_{sheet}$ times the footprint width. Unlike fins, the sheet width $W_{NS}$ can be chosen continuously, so the drive strength can be tuned for each transistor rather than in whole-fin steps (see the Fin Field-Effect Transistor page). The cost is a larger ${\lambda }_{NS}$ than for a wire of the same thickness because the wide dimension is less tightly controlled, so $T_{NS}$ and $W_{NS}$ must be chosen together. Reference: N. Loubet et al., “Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET,” Symp. VLSI Technology, 2017.

Ques: What limits how many nanosheets can be stacked?

Each added sheet increases the gated width and drive current but also the stack height $H_{stack}=N_{sheet}{T}_{NS}+(N_{sheet}-1)S_{NS}$, and the spacing $S_{NS}$ between sheets cannot fall below about $2(t_{ox}+t_m)$ because the gate oxide and work-function metal must fit in the gap on both facing surfaces. A taller stack makes the etch and fill steps harder, increases the parasitic capacitance between the gate and the source/drain regions, and weakens the control of the lowest sheet and of any parasitic channel at the bottom. The usual practical numbers of sheets are therefore a few (about three to four), with the gain in drive current balanced against the extra height and capacitance. Reference: N. Loubet et al., Symp. VLSI Technology, 2017.

Ques: What problems do the forksheet and the CFET address?

In a standard nanosheet layout the n-type and p-type transistors sit side by side and must be separated by enough space to accommodate the gate material between them, which sets the cell height. The forksheet replaces this space with a thin dielectric wall that separates the two devices, so they can be placed closer together, at the price of one ungated edge per sheet: the perimeter drops to $W_{eff,fork}=2W_{NS}+T_{NS}$ and the natural length is that of a three-gated structure, intermediate between the double-gate and full nanosheet values. The CFET goes further by placing the n-type sheet stack directly above the p-type stack, so ideally a complementary pair occupies about half the footprint, $A_{CFET}\approx A_{pair}/2$, but the total height $H_{CFET}=H_n+t_{sep}+H_p$ and the routing of contacts between the two levels become the main challenges. Reference: H. Weckx et al., “Novel forksheet device architecture as ultimate logic scaling device towards 2nm,” IEEE Int. Electron Devices Meeting, 2019; J. Ryckaert et al., “The complementary FET (CFET) for CMOS scaling beyond N3,” Symp. VLSI Technology, 2018.

Ques: How do quantum confinement and variability enter the gate-all-around device?

The sheets or wires are only a few nanometers thick, so carriers occupy discrete subbands and the threshold shifts upward by about $E_1/q$ for a wire, $E_1=j_{0,1}^2{\hslash }^2/(2m^{\ast }{R}^2)$, and by $E_{11}/q$ for a sheet. Since these shifts scale as the inverse square of the thickness, the threshold sensitivity $d{V}_{TH}/d{T}_{NS}\approx -{\pi }^2{\hslash }^2/(q{m}^{\ast }{T}_{NS}^3)$ grows rapidly as the sheets are thinned, and a fraction of a nanometer of thickness variation, such as from the etch that releases the sheets, produces a noticeable threshold spread. Controlling sheet thickness is consequently the main process-control requirement of these devices. Reference: J.-P. Colinge, FinFETs and Other Multi-Gate Transistors, Springer, 2008.

Related pages in this vault: Tri-Gate MOSFET, Fin Field Effect Transistor (FinFET), Double-Gate MOSFET, Long Channel MOSFET, Junctionless Transistor, Multi-Gate Models (BSIM-CMG and BSIM-IMG), CMOS Logic Transistors.