Tri-Gate MOSFET

1. Theory

• Definition: A tri-gate MOSFET is a transistor whose rectangular silicon body is gated on its top and both sidewalls, with the bottom resting on insulator or isolation.
• Between double-gate and GAA: It has three gated faces, sitting between the double-gate (two faces) and gate-all-around (all faces) structures.
• Relation to FinFET: Disabling the top gate with a thick hard mask reduces it to the classic FinFET.
• Effective width: The gated perimeter $W_{eff}=W_{Si}+2H_{Si}$ carries current, far more than the footprint width for a tall body.
• Natural length: ${\lambda }_{tri}$ combines the sidewall double gate across $W_{Si}$ and the top gate over $H_{Si}$; more gated faces give a shorter $\lambda$.
• Crystal-plane mobility: Top (100) and sidewall (110) planes have different mobilities, so the effective mobility is a perimeter-weighted average.
• 2D quantum confinement: Confinement in both width and height raises $V_{TH}$ by $E_{11}/q$, making it sensitive to both dimensions.

2. Working Principle

• Three-sided gate control: The gate shields the channel from the drain on three faces, suppressing DIBL and roll-off as $\exp (-L/2{\lambda }_{tri})$.
• Body shape trade-off: A tall, narrow body behaves almost like a double gate; a wide, short body behaves like a single gate.
• Drive current: Inversion layers form on all three faces, giving high current per unit layout area.
• Near-ideal swing: An undoped, fully depleted body approaches 60 mV/dec in long channels.
• Corner effects: Corners are controlled by two faces and invert first, causing a subthreshold hump and oxide stress; rounded corners reduce this.
• Variability: Small width or height variations shift $V_{TH}$ strongly through confinement.

3. Applications

• High-performance microprocessors: Introduced in volume production at the 22 nm node and used in subsequent CPU generations.
• Leading-edge logic and SRAM: Low-leakage, high-drive transistors for advanced-node processors and caches.

Name	Formula	Related Formulae	Variables/Constants
Effective channel width	$W_{eff}=W_{Si}+2H_{Si}$	$\begin{array}{r}{W}_{eff}=2H_{Si}\text{(top gate disabled)}\\ \text{(see Fin Field-Effect Transistor page)}\end{array}$	$\begin{array}{r}{W}_{eff}:\text{total gated perimeter that carries}\\ \text{current}\end{array}$ $\begin{array}{r}{W}_{Si},H_{Si}:\text{width and height of the}\\ \text{silicon body}\end{array}$
Width-weighted mobility	${\mu }_{eff}=\frac{W_{Si}{\mu }_{top}+2H_{Si}{\mu }_{side}}{W_{Si}+2H_{Si}}$	$\begin{array}{r}{\mu }_{top},{\mu }_{side}:\text{mobilities on the top and}\\ \text{sidewall crystal planes}\end{array}$	$\begin{array}{r}\text{(for a (100) wafer with the channel along}\\ ⟨110⟩,\text{the top is a (100) plane and}\\ \text{the sidewalls are (110) planes, whose}\\ \text{electron and hole mobilities differ)}\end{array}$
Natural length (tri-gate)	${\lambda }_{tri}={\left[\frac{{\epsilon }_{ox}}{{\epsilon }_s{t}_{ox}}\left(\frac{2}{W_{Si}}+\frac{1}{H_{Si}}\right)\right]}^{-1/2}$	$\begin{array}{r}{\lambda }_N=\sqrt{\frac{{\epsilon }_s}{N{\epsilon }_{ox}}{t}_{Si}{t}_{ox}}\\ N=3\text{for}{W}_{Si}=H_{Si}=t_{Si}\end{array}$	$\begin{array}{r}{\lambda }_{tri}:\text{natural length of the tri-gate}\\ \text{structure}\end{array}$ $\begin{array}{r}\text{(approximate: the two sidewall gates}\\ \text{act as a double gate across}{W}_{Si}\text{and the}\\ \text{top gate as a single gate over}{H}_{Si}\text{; the}\\ \text{inverse squares are added)}\end{array}$ $\begin{array}{r}\text{(limits:}{H}_{Si}\to \infty \text{gives the double-gate}\\ \text{value,}{W}_{Si}\to \infty \text{the single-gate value)}\end{array}$
Short-channel behavior and gate-length rule	$\Delta V_{TH},{\eta }_{DIBL}\propto \exp \left(-\frac{L}{2{\lambda }_{tri}}\right)$	$\begin{array}{r}L\gtrsim 5\text{to}6{\lambda }_{tri}\text{(rule of thumb)}\\ \text{(see Double-Gate MOSFET page)}\end{array}$	$\begin{array}{r}\text{(same functional form as the double-gate}\\ \text{page with}\lambda \text{replaced by}{\lambda }_{tri}\text{)}\end{array}$
Two-dimensional quantum confinement	$E_{11}=\frac{{\pi }^2{\hslash }^2}{2m^{\ast }}\left(\frac{1}{W_{Si}^2}+\frac{1}{H_{Si}^2}\right)$	$\Delta V_{TH}\approx \frac{E_{11}}{q}$	$\begin{array}{r}{E}_{11}:\text{lowest subband energy of the}\\ \text{rectangular body (infinite-well}\\ \text{approximation)}\end{array}$ $\begin{array}{r}{m}^{\ast }:\text{effective mass}\\ \text{(a single value is used here;}\\ \text{different directions can have different}\\ \text{masses)}\end{array}$
Drain current (long channel, strong inversion)	$I_{Dsat}=\frac{{\mu }_{eff}{C}_{ox}}{2m}\frac{W_{eff}}{L}{\left(V_{GS}-V_{TH}\right)}^2$	$\begin{array}{r}m\approx 1\\ \text{(see Long Channel MOSFET page)}\end{array}$	$\begin{array}{r}\text{(the width of the long-channel expression}\\ \text{is replaced by the gated perimeter}{W}_{eff}\text{)}\end{array}$
Ideal long-channel subthreshold swing	$S\to \ln (10)\frac{k_{B}T}{q}\approx 60mV/dec$	$\begin{array}{r}L\gg {\lambda }_{tri}\\ \text{(see Double-Gate MOSFET page)}\end{array}$	$\begin{array}{r}\text{(an undoped body has no depletion-}\\ \text{capacitance divider, so the swing}\\ \text{approaches the thermal limit)}\end{array}$ $k_B:Boltzmannconstant$

Important Questions

Ques: Why does a tri-gate give better short-channel control than a planar device, and how does it compare with the double-gate and gate-all-around cases?

Each gated face shields the channel from the drain’s field, and the combined effect appears in the natural length. In the limiting case of equal width and height the effective number of gates is $N=3$, so ${\lambda }_N=\sqrt{{\epsilon }_s{t}_{Si}{t}_{ox}/(N{\epsilon }_{ox})}$ lies between the double-gate ($N=2$) and the fully wrapped ($N=4$ for a rectangular body) values: the more faces that are gated, the shorter $\lambda$ becomes and the shorter the gate length that can be used for the same $L/\lambda$ ratio. The inverse-square-sum expression for ${\lambda }_{tri}$ makes the trade-off explicit, because a tall, narrow body behaves almost as a double gate (the top gate matters little), while a wide, short body behaves like a single gate. Reference: J.-T. Park and J.-P. Colinge, “Multiple-gate SOI MOSFETs: device design guidelines,” IEEE Trans. Electron Devices 49, 2222 (2002); J.-P. Colinge, FinFETs and Other Multi-Gate Transistors, Springer, 2008.

Ques: Why does the effective width include the sidewalls, and why does the mobility have to be weighted?

Current flows in an inversion layer along every gated face, so the transistor’s drive is proportional to the gated perimeter $W_{eff}=W_{Si}+2H_{Si}$, which for a tall body is far more than its footprint width $W_{Si}$; this is the origin of the large drive current per layout area of fin-type devices. The faces are different crystal planes, however, so electron and hole mobilities on the top and sidewalls generally differ, and the current has to be weighted by the perimeter share of each plane, ${\mu }_{eff}=(W_{Si}{\mu }_{top}+2H_{Si}{\mu }_{side})/W_{eff}$. This is also why sidewall orientation is a design choice: a (110) sidewall favors holes at the expense of electrons relative to (100). Reference: J.-P. Colinge, FinFETs and Other Multi-Gate Transistors, Springer, 2008.

Ques: What are corner effects in a tri-gate, and why do designers round the corners?

Near each corner of the rectangular body two gated faces meet, so the corner is controlled by two gates and its potential responds more strongly to the gate than the flat faces do. The corner therefore inverts first, at a lower gate voltage, and this produces a lower-threshold parasitic channel with extra subthreshold current (a hump in the subthreshold characteristic), while the field concentration also worsens oxide reliability. Rounding the corners with a finite radius spreads the field, reduces this lower-threshold region, and makes the threshold more uniform around the perimeter, at the cost of a slight loss of effective width. Reference: J.-P. Colinge, FinFETs and Other Multi-Gate Transistors, Springer, 2008; B.S. Doyle et al., “High performance fully-depleted tri-gate CMOS transistors,” IEEE Electron Device Lett. 24, 263 (2003).

Ques: How does quantum confinement affect the threshold voltage and its variability?

In a body only a few nanometers across, carriers are confined in two directions and occupy discrete energy levels, so the threshold increases by about $E_{11}/q$, with $E_{11}=({\pi }^2{\hslash }^2/2m^{\ast })(1/W_{Si}^2+1/H_{Si}^2)$. Because this shift scales as the inverse square of each dimension, small variations in width or height from lithography or edge roughness produce large threshold variations, with sensitivity growing as the body is thinned. Keeping the body dimensions uniform is therefore one of the main manufacturing requirements of these devices. Reference: J.-P. Colinge, FinFETs and Other Multi-Gate Transistors, Springer, 2008.

Related pages in this vault: Fin Field Effect Transistor (FinFET), Double-Gate MOSFET, Gate All Around Field Effect Transistor (GAAFET), Long Channel MOSFET, Junctionless Transistor, Static Random Access Memory (SRAM), Static and Dynamic Random Access Memory (SRAM and DRAM), Multi-Gate Models (BSIM-CMG and BSIM-IMG), CMOS Logic Transistors, Plasma and Radical Oxidation Tool, Plasma Immersion Ion Implanter.